Intel Takes 32 nm PMOS to Record Levels

[Idontcare]

Intel Takes 32 nm PMOS to Record Levels

Intel Corp. presented details on its 32 nm logic technology at the International Electron Devices Meeting (IEDM), reporting that its fourth-generation strain techniques have boosted the PMOS performance to a historic point. "For the first time, linear drive currents on the PMOS have overtaken NMOS," said Paul Packan, 32 and 15 nm technology programs manager.

For the oft-quoted saturated drive current, the 32 nm NMOS value remains higher, at 1.62 mA/μm Idsat compared with 1.37 mA/μm for the 32 nm PMOS transistor. Packan said the PMOS linear drive current (ldlin) reached 0.24 mA/μm, a 35% improvement over the 45 nm PMOS transistor. The NMOS device Idlin gained a 20% improvement, partly from a raised source-drain architecture, reaching a linear drive current of 0.231 mA/μm. Linear drive current is important because transistors rarely get to full saturation, making Idlin a meaningful metric for real-world device operation.

With NMOS and PMOS now in rough parity, designers can adjust the size of the PMOS transistors to their needs, said Mark Bohr, a senior fellow at Intel. "For many generations, there was a 2:1 ratio between the NMOS and PMOS," largely caused by inherently different mobilities between electrons and holes. "At the 32 nm generation, our saturation and linear drive currents are closer to being matched; we are getting very close." That means for the Westmere processor Intel designers could create circuits with smaller PMOS transistors in some cases, Bohr said.

http://www.semiconductor.net/article/439536-Intel_Takes_32_nm_PMOS_to_Record_Levels-full.php

If you look closely, the very reason Moore's Law exists is buried in the last sentence of the linked article

 

[myocardia]

If you look closely, the very reason Moore's Law exists is buried in the last sentence of the linked article

I didn't realize the reason for Moore's Law existing was a secret. I also always thought exactly the same way about video card performance, although I'm sure the vast majority of teenagers here will disagree.

 

[jvroig]

Not only does Intel want to remain ahead of its MPU competition, its computer customers need faster MPUs every two years so they can sell new systems to their customers, he said.

:thumbsup: Priceless. Not surprising in itself, just surprising it would be blatantly written like that without any attempt at justification like "the world needs faster computers, researchers need faster tools for simulation, somebody's got to cure cancer, etc".

 

[Daedalus685]

Heh, money money...

I wonder how stuborn people have to get before they try to quadruple performance every couple of years.

I wonder how Ray Kurzweil would respond to that.. Though accerlated growth is accelerated growth.. whether driven by the lust for inovation or the almighty buck..

 

[Idontcare]

I wonder how stuborn people have to get before they try to quadruple performance every couple of years.

Looking at the direction of Intel's ISA extensions in Westmere, I would say security is the next killer app and we are going to see more and more compute-intensive software applications coming to the market.

So fear will drive the purchasing cycle for the next wave of killer apps, which will then demand continued performance improvements to push the inconvenience of security back down to background levels. (SSD's and anti-virus scans for example)

 

[TuxDave]

With NMOS and PMOS now in rough parity, designers can adjust the size of the PMOS transistors to their needs, said Mark Bohr, a senior fellow at Intel. "For many generations, there was a 2:1 ratio between the NMOS and PMOS," largely caused by inherently different mobilities between electrons and holes. "At the 32 nm generation, our saturation and linear drive currents are closer to being matched; we are getting very close."

Imagine my surprise when I was told I could start using higher count stacked PMOS gates with less penalty (let alone the idea that the 2:1 ratio was already trending towards 1:1 when I first got hired which was enough of a shocker for a fresh college graduate)

 

[Idontcare]

Imagine my surprise when I was told I could start using higher count stacked PMOS gates with less penalty (let alone the idea that the 2:1 ratio was already trending towards 1:1 when I first got hired which was enough of a shocker for a fresh college graduate)

I have to imagine your colleagues who work for other employers in the industry are just a bit jealous of this added degree of flexibility you have at your disposal.

I'm really interested to see what comes of this. Sure the scientist/geek in me can appreciate the coolness of this shift in device physics for that reason alone, but what will it actually bring to the consumer space?

Faster clockspeeds than otherwise would have been? Cooler chips than otherwise would have been? Cheaper chips than otherwise would have been?

Consider that for all the sexy technology appeal that first-gen 45nm HK/MG brought to the headlines at the time, the resultant products aren't heads-and-shoulders above what AMD brought to the market using standard 2:1 NMOSMOS Idrive xtors and traditional doped-poly/SiON gate stack integration.

I'm waiting for coolness at the device physics level to translate into awesome, otherwise unachievable, products at the consumer level. Presumably there will be a delay in the adoption of the newest tricks made available, after all risk versus reward is a pervasive mentality at Intel.

But presumably at some point in the near future (5yrs tops) I am expecting some really cool golly-gee-willikers kind of CMOS chips popping out that could not have been achieved without this technology...otherwise the hype in mainstream press is kinda pointless. Not that that ever stopped IBM though

 

[soccerballtux]

Good article, favorites here:

Although Intel remains on a Moore's Law pace in terms of contacted gate pitch scaling, with a 112.5 nm pitch, shrinking is no longer delivering the speed improvements seen in past generations, Packan said. With smaller dimensions, less material can be deposited to add strain. And threshold voltages have crept up slightly in recent years at the same Ioff levels.

and

He estimated that were it not for the additional benefits of higher strain, performance actually would have declined for the 32 nm transistors. One reason, Bohr said, is that to counter short channel effects in the aggressively scaled gates the channel must receive higher dopant levels, causing threshold voltages to rise and slowing down the transistor.

Good read.

 

[soccerballtux]

Heh, money money...

I wonder how stuborn people have to get before they try to quadruple performance every couple of years.

I wonder how Ray Kurzweil would respond to that.. Though accerlated growth is accelerated growth.. whether driven by the lust for inovation or the almighty buck..

Ray did not understand how shrinking process nodes lead to exponential size reduction.
He was using one dimensional thinking

 

[soccerballtux]

Faster clockspeeds than otherwise would have been? Cooler chips than otherwise would have been? Cheaper chips than otherwise would have been?

I saw it as more of a technical achievement than something that will actually drive performance. But maybe that's because I"m not thinking outside the box enough. Methinks you don't have any ideas either?

 

[IntelUser2000]

I see it more as in terms of "to stop hindering the progress of technology" rather than changes we can see easily.

Like how developments like better programmability in GPUs are insignificant to consumers, but overall its better for the industry, and indirectly better for us as well. Without those significant "revolutionary changes" the advances would slowly stop.

 

[WhoBeDaPlaya]

Maybe I'm not reading it closely enough, but dayum, now you're saying that we no longer have to size our PMOS widths 2-3x that of NMOSes? This will definitely alleviate parasitic capacitance concerns with static CMOS, not to mention make it easier to design faster analog circuits like op-amps.

 

[Nemesis 1]

Another great post by IDC . I have one question. Whos transitors will be smaller Intels 32nm or others 28nm . I know ans. I just think you should adderess it .

The other thing I have is this Intels 45nm was done using the old tried and true with addition of high k/Metal gates . AMDS 45 was using immersion . so your comparsion isn't to good . At 32nm for Intel Immersion is used lets see how AMDs stacks up against intels gate last comparred to AMDS gate first.

 

[Idontcare]

Maybe I'm not reading it closely enough, but dayum, now you're saying that we no longer have to size our PMOS widths 2-3x that of NMOSes? This will definitely alleviate parasitic capacitance concerns with static CMOS, not to mention make it easier to design faster analog circuits like op-amps.

Exactly. From the device physics standpoint having Idrives this high is awesome, and having the ratios all that much closer to unity is great.

I can't remember the quote exactly but when Intel debuted their 45nm HKMG and the PMOS took such an exceptional advancement forward and beta ratio's nose-dived one of their execs (Otellini? Gelsinger? Ratner?) said publicly that it enabled them to tell their design engineers to do some wonderful things that we wouldn't see for a couple years (from then).

Now there is the obvious list of "wonderful things" you would do as a design engineer if/when given PMOS xtors that rival NMOS drive currents (linear or sat) but the net result of those implementations are otherwise smaller dies for the same xtor count with lower leakage (both static and dynamic).

But I wouldn't categorize that as being "wonderful", so I am curious to see what else having a 1:1 beta ratio is enabling design engineers to do. My experience in this field is limited.

Another great post by IDC . I have one question. Whos transitors will be smaller Intels 32nm or others 28nm . I know ans. I just think you should adderess it .

The other thing I have is this Intels 45nm was done using the old tried and true with addition of high k/Metal gates . AMDS 45 was using immersion . so your comparison isn't to good . At 32nm for Intel Immersion is used lets see how AMDs stacks up against Intel's gate last compared to AMDS gate first.

Are you asking about design rule dimensions Nemesis? As in "who will have the smallest channel width transistor?" or who will have the tightest gate contact pitch? Logic or sram or just in general?

I would be surprised if Intel has the smallest Lg at either 32nm or 28nm, one thing that happened at 45nm with their introducing HKMG is they reversed the decade long trend where the channel width was ~1/2 the value the of the node label.

http://www.chipworks.com/blogs.aspx?blogmonth=10&blogyear=2007&blogid=86

Now it is more 1:1. The non-HKMG guys still have to scale their Lg at about 1/2 the nominal node value to get their drive currents up.

But Lg doesn't determine contact pitch on its own, contact pitch must accomodate Lg so a larger Lg tends to drive a large contact pitch (which determines things like sram density). So I won't be surprised if Intel's contact pitch is larger than the competition as well.

Only time (and Chipworks ) will tell!

 

[TuxDave]

I have to imagine your colleagues who work for other employers in the industry are just a bit jealous of this added degree of flexibility you have at your disposal.

I'm really interested to see what comes of this. Sure the scientist/geek in me can appreciate the coolness of this shift in device physics for that reason alone, but what will it actually bring to the consumer space?

Faster clockspeeds than otherwise would have been? Cooler chips than otherwise would have been? Cheaper chips than otherwise would have been?

While I'm still mostly in the digital space, the basic answer is yes that things will just get cooler and faster. The other way of looking at it is there are some features that were too crappily slow that we can start considering them again. Now if only some miracle could save me from these darn slow wires.