Intel Skylake / Kaby Lake / Coffee Lake Thread - Coffee Lake-S specs out (page 554)

Discussion in 'CPUs and Overclocking' started by Sweepr, Apr 16, 2015.

  1. imported_ats

    imported_ats Senior member

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    1) maybe, maybe not. Variance works off of a lot of different factors
    2) Intel historically has had absolutely insane yields on their server parts. The large server dies have an absolutely insane lvl of redundancy and harvest ability. I think you severely underestimate the yields on Intel server parts.
    3) And no one would want to. 10Gbe? It is all but dead in the server market. New deployments are being done with 40Gbe/25Gbe/50Gbe/100Gbe. USB 3.1 in the server space??? 128 lanes of PCIe is simply unneeded in this space or pretty much any other per socket (and before you scream about NVMe, no one wants to route that many lanes from the socket to a backplane, real NVMe deployment are done with PCIe switch chips). And I'm pretty sure that Xeons will support more memory per socket.

    The MCM really doesn't buy you anything over monolithic except not having to tape out a separate die. And that's the reason that AMD is doing it, because they are resource constrained, not because it is better. If they weren't resource constrained, they be doing a larger monolithic die.
     
  2. lolfail9001

    lolfail9001 Golden Member

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    Care for a signature bet?
    And what is your source, dare i ask.

    P. S. By the way, seriously, would not 10GbE be pretty outdated at this point, you know.
     
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  3. krumme

    krumme Diamond Member

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    For servers. Why is scalability from eg 8 to 32 cores especially interesting? Why not 357 to 1478,5?
    I mean in the grander scheme fabric performance must be there all over. Be it ccx, mcm, 2 socket ....->
    The perf and safety of the protocol must be allover.
    We have been at "true quadcore". Who cares from a customer perspective. What matter is real world tangible benefit. You buy performance not cores.
     
  4. itsmydamnation

    itsmydamnation Golden Member

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    And is significantly easier to bin based off ( high leakage/low leakage) because there is simply less transistor variance. The funny thing is Intel have said in the future they are going to start doing the same thing but with small interposes, but keep fighting that fight right up until intel does it, then just pretend you always thought it was awesome.

    Then why do they never sell 24 core Broadwell EP's why is skylake-SP only upto 28core..... go think about that for a minute. AMD can pick and match chips as you can see so far amd has had no problem delivering truckloads of 8 core chips.

    Funny how you pick and choose to ignore the stuff that invalidates your point like the fact neither intel or amd can build what is in a 32core Naples Processor on a single monolithic die today.......


    now i know you guys have no idea what your talking about........

    10Gb/e = 10.3125G SerDes
    40Gb/e = 4x 10.3125G SerDes

    25Gb/e = 25.78125G SerDes
    50Gb/e = 2x 25.78125G SerDes
    100Gb/e = 4x 25.78125G SerDes

    Now as of right this second the two most common TOR ports found in switches are either :

    1. 10/25gbe switchable SFP+
    2. 10/25/40 switchable QSFP

    SO can you guess what 16x 10gbe interfaces can be physically pinned out as..... thats right 4x 40Gb/e, even if for some reason there is a limitation not allowing Zepplin to at layer 1 create a 40Gbe interface it still isn't a problem because QSFP ports can break out into 4x10gbe and then you can just use LACP. If you really need to you can 8x 10gbe LACP into TOR 1 and the other 8x into TOR 2. Now your done.

    my Second point is no one is using 100Gb/e as access ports to Servers, 100Gb/e is uplink only, even the biggest switch ASIC i know of ASE-2/tomahawk is "only" 3.2/6.4 Tbps of throughput so there isn't enough bandwidth for it, then there is the fact you still have to get that traffic EAST/WEST/NORTH.

    next time you want to try and make a BS point like that dont do it to a guy who designs highend networks for a living :)

    edit: also most common server connectivity sold to enterprise is 10Gbe by a very long way.


    So on PCIe lanes only because they have no other option, what you just said is everyone loves being bottlenecked.
    So the funny thing is, I have been talking to nutanix engineers and they are really excited about what a 24/32 core naples with 128 lanes will mean for them, I better go inform them that they are wrong, cuz they dont understand hyper-converged........

    Based off what? Your ignoring the fact that even if it can it will be at significantly lower throughput ( two less channels, lower max freq and then if they going 18dimms a proc it will run even slower).
     
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  5. coercitiv

    coercitiv Platinum Member

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    @imported_ats - I generally appreciate your posts, but this makes no sense. You may argue there are other advantages in large monolithic dies that offset the loss associated with transistor variance (especially with a mature process), but to somehow suggest that a small die may have higher transistor variance than a large die on the same process is not related to science in any way.
     
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  6. imported_ats

    imported_ats Senior member

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    No, Intel hasn't said that, they are planning to do something significantly different.

    Because they make more money selling them as -EX parts. Simple really. Skylake is upto X because that's what they decided was a good intercept point between MT perf, ST perf, die size, and power.




    SERDES doesn't buy shit without the supporting control and hardware. 40Gbe takes significantly more resources than 4x10. And LACP isn't 40g. Secondly, servers have moved ALREADY from 40g per server to high bandwidths. most are looking at 50 to 100 INTO TOR these day for wide scale deployments. And the 6.4Tbps switches allow 64x100g which surprise, work just fine for TOR as well as everything else. 64p building blocks for instance form the entire networking infrastructure at facebook.

    Sure because they'll get better pricing from Intel. Not because that many PCIe are actually useful. And no, it isn't a bottleneck. No one buy all SSD is buying them for sequential performance, they are buying for IOPS. Hell the only drive that even comes close to saturating 2xPCIe 3 in realistic scenarios is the P4800x. AKA, the trunk bandwidth can be over-subscribed 2x with a drive ~5x faster than anything else out these in realistic workloads with no effect.


    Based on not being ignorant. Intel will likely be offering effectively 12 channels per socket. And it is unlikely to be at lower throughput either.
     
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  7. imported_ats

    imported_ats Senior member

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    Variance is based of a variety of factors. The variance we are interested in is die location independent variance. Its a pretty chaotic effect and has as much to with layout of the design/masks and physics interactions than anything else. AKA, die size is pretty much immaterial. And note, I merely said that saying variance will be better for the moderate sized zepplin die isn't valid. I think Intel likely has much better process in general and location independent variance.
     
  8. coercitiv

    coercitiv Platinum Member

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    It was my impression we were leaving process differences aside for the sake of this discussion, and comparing MCM vs. monolithic on equal grounds (same process, same vendor etc). As mentioned above, Intel also has plans for migrating their products towards a more modular approach.

    Do you think Intel's EMIB products will be inherently inferior vs. their monolithic counterparts?
     
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  9. Arachnotronic

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    Intel's Purley platform (aka Skylake Xeon) has been planned for mid-2017 for a long time and on Intel's most recent earnings call they said Purley is coming mid-summer. It doesn't look to me like anything is being pulled in on the Xeon front.

    Intel's schedules with Xeon are more driven by customer demands rather than trying to react to AMD or any other competitor.
     
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  10. TemjinGold

    TemjinGold Diamond Member

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    With all the rampant speculation going on about how great Intel will be, I'm wondering why the Intel folks here think CFL will be such a monster when the following seems true:

    1) Intel did not take AMD seriously all the way until AFTER Ryzen launched and sold.

    2) From the time Intel took AMD seriously, they could not have had enough time to bring out something smashingly new.

    3) Absent Ryzen's success, Intel has been content with just minor incremental bumps with each release.

    This CFL thing would've been coming out even if Ryzen did not exist, it just would've been coming out slower. Ryzen did not change what CFL is (there simply isn't enough time), only how soon it will hit market. Intel has been VERY incrementally bumping things along since Sandy Bridge. Why do you guys think all of a sudden that will change?

    I used to own Intel, I have a Ryzen now. I won't sit here and tell you AMD will reign supreme forever. Intel, with its massive resources, will eventually put out something that slaughters AMD's best. But I highly doubt that's going to be this year.

    On a side note, I recall first seeing the rumor of X399 but recently it's spoken of as a sure thing. Has it been officially confirmed that there's an X399 16c monster from AMD coming?
     
  11. lolfail9001

    lolfail9001 Golden Member

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    Because there is no reason to suspect it will be anything but a 6 core with OC clocks very close to OC 7700k clocks. If you think that qualifies as a monster, then why do you wonder.

    And really, Intel could only fool idiots with new Skylake stepping without any real improvements for so long, they had to bump core counts at this point.
     
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  12. xdfg

    xdfg Member

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    It's really simple. Intel spends so much time planning a hugeass monolithic die, gets shit yields due to all the wafer defects, and when it comes out, it is what it is. Meanwhile, AMD can cheaply produce 8-core dies with high yield, due to the much lower area, then connect them into an N+1 core configuration as soon as Intel announces anything. What can Intel do about it? Nothing, since it'll take them years to design another inefficient monolithic chip.

    Ryzen 8 cores: $320
    Ryzen 16 cores: $640
    Ryzen 32 cores: $1280

    That's the beauty of AMD's superior MCM efficiency. Since they just connect more of the same chip, the cost scales linearly with cores instead of exponentially with Intel. Just look at the Skylake-SP prices and you can confirm for yourself. $12000 for only 28 cores! Even if we add a pessimistic 100% enterprise markup for AMD, they're still undercutting Intel by almost 70%.

    On top of that, we have the superior energy efficiency of Ryzen. Look at the leaks for the Xeon Platinum 8180; it's got a scorching 250 W TDP for 28 cores at 2.5 GHz. Just by scaling from the R7 1700, we're looking at 32 cores at 3 GHz with 260 W (4 * 65), before accounting for the extra efficiency from running at lower clocks that Stilts already proved. The performance per dollar and performance per watt will be absolutely dominance, since Zen is already performing 25% better than Haswell in IPC (compared to regressing IPC in Skylake!) as shown by Markfw.

    TLDR: Intel server monopoly is destined for the history books.




    Trolling isn't allowed.


    esquared
    Anandtech Forum Director
     
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  13. imported_ats

    imported_ats Senior member

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    I don't know, the only announced EMIB part isn't use the MCM for logic but for I/O flexibility which is a pretty decent reason. AKA, EMIB is giving the design something that simply wouldn't of been practical or possible in a monolithic die.
     
  14. nvgpu

    nvgpu Senior member

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    You can ignore a certain liar, because the 28 core Xeon Platinum is not 250W TDP as claimed, ignorant people don't even know the real specs but blatantly post lies here making themselves look foolish. ;)

    http://i.imgur.com/tk3dbCZ.png

    Saved the screenshot in case of edits to cover their tracks.



    Insults are not allowed in tech.


    esquared
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    #10289 nvgpu, Apr 30, 2017
    Last edited by a moderator: Apr 30, 2017
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  15. imported_ats

    imported_ats Senior member

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    Intel's yields on Xeon designs have typically been among the highest yield of any parts of any size in the entire industry. The idea that die size determines yield is and always has been completely bogus. What determines yield is non-fixable defects. Also your idea of what's required to do a MCM is sorely lacking. Suffice to say that MCM doesn't do jack to speed up turnaround and in many cases actually slows down the speed of design.

    Anyone who believes that pricing progression is completely ignorant of the industry.

    Econ 101, Price != Cost, Cost != Price.

    Or you know, keep comparing things you don't under stand. 4x is what you think it will be? Lol, you are leaving out a whole lot, like ~4x the PCIe, all the intra and inter socket interconnects, etc. And Markfw hasn't shown any such data in any way, shape, or form.
     
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  16. xdfg

    xdfg Member

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    You can look up the numbers yourself. Every claim I have ever made in this thread is backed by hard facts, usually posted just pages ago. I can't help you if you just want to stick your head in the sand.

    Cost determines the lower bound of price, and based on superior MCM scaling, we can already see that floor is extremely low. On the other hand, how much room does Intel have to play with prices on their ridiculous monolothic dies?

    You can go only a few pages back to see the evidence from Markfw, or just one thread over for the Stilts power efficiency numbers. Besides that, you seem to not understand arithmetic. If AMD quadruples everything with Naples, that would be 4x the power, which is an upper bound, so we're not even accounting for any optimizations that would make the actual power less than the 4x figure.
     
    #10291 xdfg, Apr 30, 2017
    Last edited: Apr 30, 2017
  17. lolfail9001

    lolfail9001 Golden Member

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    Source.

    Oh, you cannot provide it either? How sad.

    And yeah, Sandra numbers are bogus.
     
  18. nvgpu

    nvgpu Senior member

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    Nowhere on Sisoft's page it says 250W TDP, are you off your medications or what? Seeing your post history tells it all, registered in March 2017, attacking Intel every post with blatant lies, probably a paid AMD Red Team member. Ignored.




    Calling people shills isn't allowed.


    esquared
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    #10293 nvgpu, Apr 30, 2017
    Last edited by a moderator: Apr 30, 2017
  19. IEC

    IEC Lifer

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    Re: the pricing and the TDP, both are clearly mentioned in the TweakTown article. And the poster above transposed the last two digits on the TDP; it is supposedly 205W not 250W.

    Source: http://www.tweaktown.com/news/57293/intels-new-xeon-rocks-28c-56t-costs-over-12-000/index.html

    Being blunter than usual here, but I didn't come into this thread to watch purse swinging and cat fights. It would be almost entertaining if it wasn't so sad. Grow up, kiddos.
     
  20. Shivansps

    Shivansps Golden Member

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    You are not seeing maybe because you are part of them. (by the way you decided to write that).

    The diference here with A64 is very very simple, Intel do not need to match core counts, because they still have IPC and core clock speed avantage, on mainstream. Not sure why you even mention the 7700K no one on its right mind whould buy one today.
    Also i think the IPC difference is bigger with newer instructions for some reason, for example, HEVC and H264 encoding, witch are fully threaded and uses AVX, the difference is way less than for example in 7-zip that it does not even use SSE, is pure int ops.
    [​IMG]
    [​IMG]
    [​IMG]

    On servers will know once Skylake-X/SP is launched, way too hard to know what their performance will be, with full 8-way and 1MB L2. And it remains to be seem what happens with AVX-512, it may be limited to LGA 3647 cpus.
     
  21. DrMrLordX

    DrMrLordX Diamond Member

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    Naples is a threat in 1P and 2P configurations. Others have touched on the point but I'll repeat it here for emphasis.

    Also, I do not think we'll have to worry that much about Naples' performance due to fabric speeds, but I could be wrong. Again, look to the application itself and ask: how often are you going to come under the total thread count of the CPU? How often are you going to get inter-thread communication? Is that inter-thread communication already a problem on multi-socket systems? In other words, I would expect that the CCX strategy will work better with multisocket-friendly applications than it will . . . games, for example.

    Nobody is going to buy Naples to run Starcraft II

    As for Purley, it has a launch that is set in stone, so I do not expect Intel to do anything but maybe tweak prices in response to X399. We will not see the price reductions - if any - publicly. Intel and/or OEMs/ODMs will adjust prices on a deal-by-deal basis to complete sales where necessary whenever the procurement guy starts to say, "you know, we've been giving those Naples systems a hard look and . . ." .
     
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  22. xdfg

    xdfg Member

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    Pretty much every relevant player in datacenter is using VMs now, so it's a trivial matter of just setting the VM size so that it fits nicely in 8 core units. In servers, the predominant programming paradigm is multiple instances of single or low-threaded applications, so there will be no cross-chip overhead in 99% of use cases. Trying to scale a single application across a huge number of cores is definitively a consumer issue, since desktop users only ever do one thing at a time. Again, this is the brilliance of Naples MCM, which avoids all the costly and expensive internal fabrics in Intel's monolithic designs.
     
  23. Shivansps

    Shivansps Golden Member

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    Yes thats a good point there.
     
  24. Markfw

    Markfw CPU Moderator VC&G Moderator Elite Member
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    AS A MOD
    BTW, thanks for getting this thread back to a logical discussion.



    As a member:
    And incidentally, I am probably the only one here seriously interested in a new Xeon, or Naples, for my DC project work, thats the only reason I came into this thread.
     
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  25. PaulIntellini

    PaulIntellini Member

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    MCC should be 16 cores (bottom 2 rows of cores removed)