Question Intel Raptor Lake vs AMD Zen 4 vs Apple M2

[eek2121]

Yeah, so why are you comparing 7nm to 5nm? They are priced differently and one doesn't even cut into the production of the other.

Increasing the transistor count on 5nm will yield less cores per wafer than not increasing transistor count, there isn't even any room for discussion there, the die size you mention and link to doesn't even tell us if it's the same transistor count as previous zen which it very well could be.
TSMC already announced a 20% increase in all prices, if AMD increases that by another 25-35% by adding that amount of transistors more then the final price will be 45-55% higher which would be way too high.

Are you just here to troll?

The price increases for 5nm for AMD are far less than the density increase. The peak density increase of 5nm over N7 is 84% btw, with SRAM shrinking by 30%. On top of that, AMD uses custom libraries for Zen 3 that have lead to Zen 3 only being a small percentage of the density N7 is capable of.

 

[DrMrLordX]

Average is 120W vs 144W. Nothing to write home about really. While beating 5950x in plenty of light threaded workloads in both efficiency and performance.
So even handicapped by Intel in default configuration it is performing real well.

Are we discussing other benchmarks from Phoronix now? Previously we were discussing only the compiler benchmarks (for some reason).

 

[tamz_msc]

Here's something interesting that I find relevant to this discussion:

Going Armchair Quarterback on Golden Cove’s Caches

Processor speed has rapidly outpaced advances in DRAM technology, so caching strategy is a huge part of CPU performance today. A couple of articles ago, we saw Intel’s decisions with Golden C…

chipsandcheese.com

Simulating the effect of different cache hierarchies on Golden Cove. TL;DW version is this:

• C&C: Intel should lower L1D latency, even if it means decreasing capacity and associativity. My interpretation: since a smaller, faster L1D gives better performance, Zen 4 will be at an advantage here, as the leaks suggest that L1D will remain 32 KB.
• C&C: Well played, Intel. Keep using those big, relatively fast L2 caches. My interpretation: RPL bumps L2 up to 2MB according to leaks. It will have to be seen how big a latency hit that causes. Zen 4 will bump L2 to 1MB, and given AMD's track record of keeping latency tightly in check, it will be a close call as to which uarch has the better L2.
• C&C: Lower L3 latency. Consider putting the ring and L3 cache back on the core clock domain, Sandy Bridge style. That may mean dropping some power efficiency under light iGPU-only load. Or not sharing the L3 between the CPU and iGPU. But strong single-threaded performance is a traditional Intel advantage, and AMD is scary close even after Alder Lake’s release. Every little bit will matter if Intel wants to retain their traditional advantage. My interpretation: RPL doesn't stand a chance here against Zen 4, as Intel's track record with victim L3$ has been worse compared to AMD.
• C&C: If you have to choose between a bigger L2 and a lower latency L3, pick the latter. Increasing L2 cache size from 512 KB to 1280 KB sometimes produces huge hitrate increases, but is quite inconsistent. Meanwhile, a large 30 or 32 MB L3 is often enough to cover an application’s working set. My interpretation: There's no question that AMD is on the right track with Zen 3 going on to Zen 4.

C&C conclusion:

AMD’s caching strategy in Zen 3 is also superior to Intel’s. In terms of IPC gain, it’s not as good as M1’s. But it’s especially dangerous to Intel because it can run at similarly high clock speeds. That caching advantage lets AMD achieve similar performance with much smaller cores.

It’ll be interesting to see how Intel modifies their cache setup going forward. If they stay the course with high latency caches, their core design team will have to pull miracles to compensate.

 

[Henry swagger]

Here's something interesting that I find relevant to this discussion:

Going Armchair Quarterback on Golden Cove’s Caches

Processor speed has rapidly outpaced advances in DRAM technology, so caching strategy is a huge part of CPU performance today. A couple of articles ago, we saw Intel’s decisions with Golden C…

chipsandcheese.com

Simulating the effect of different cache hierarchies on Golden Cove. TL;DW version is this:

• C&C: Intel should lower L1D latency, even if it means decreasing capacity and associativity. My interpretation: since a smaller, faster L1D gives better performance, Zen 4 will be at an advantage here, as the leaks suggest that L1D will remain 32 KB.
• C&C: Well played, Intel. Keep using those big, relatively fast L2 caches. My interpretation: RPL bumps L2 up to 2MB according to leaks. It will have to be seen how big a latency hit that causes. Zen 4 will bump L2 to 1MB, and given AMD's track record of keeping latency tightly in check, it will be a close call as to which uarch has the better L2.
• C&C: Lower L3 latency. Consider putting the ring and L3 cache back on the core clock domain, Sandy Bridge style. That may mean dropping some power efficiency under light iGPU-only load. Or not sharing the L3 between the CPU and iGPU. But strong single-threaded performance is a traditional Intel advantage, and AMD is scary close even after Alder Lake’s release. Every little bit will matter if Intel wants to retain their traditional advantage. My interpretation: RPL doesn't stand a chance here against Zen 4, as Intel's track record with victim L3$ has been worse compared to AMD.
• C&C: If you have to choose between a bigger L2 and a lower latency L3, pick the latter. Increasing L2 cache size from 512 KB to 1280 KB sometimes produces huge hitrate increases, but is quite inconsistent. Meanwhile, a large 30 or 32 MB L3 is often enough to cover an application’s working set. My interpretation: There's no question that AMD is on the right track with Zen 3 going on to Zen 4.

C&C conclusion:

Armchair designer just speculating.. kmows nothing

 

[tamz_msc]

Armchair designer just speculating.. kmows nothing

What are your credentials, if I may ask?

 

[itsmydamnation]

Armchair designer just speculating.. kmows nothing

Armchair forum whore just speculating..
Kmows nothing

 

[biostud]

In gaming when using graphics settings that you would actually play with zen3=zen4=ADL=RPL, because the video card would be the limiting factor. (Unless we’re talking cs:go 1080p)

My guess is that zen4 and RPL will be pretty close in performance, but RPL will use a lot more power under full load. I can’t see how intel would bring power consumption significantly down using same process node intel7, while AMD moves from 7nm/12nm to 5nm/6nm.

In laptop M2 is going to reign supreme when it comes to performance/watt and also being very powerful, but it only matters if your work/gaming can be done on theApple platform.

 

[Henry swagger]

What are your credentials, if I may ask?

What chips has the author created to lecture what intel has created lol ?

 

[itsmydamnation]

What chips has the author created to lecture what intel has created lol ?

How about you take two minutes to look at the data they have produced and play the ball not the player?

 

[JoeRambo]

Are we discussing other benchmarks from Phoronix now? Previously we were discussing only the compiler benchmarks (for some reason).

I was respomding to Your claim:

12900k on the Linux kernel compilation bench takes 200W vs 5950X 142W and performance is a dead heat.

when actual difference in kernel compile is:

 

[DrMrLordX]

when actual difference in kernel compile is:

Well in that case, the 12900k winds up looking worse in the LLVM bench immediately below it.

Point still stands, 12900k burns more power in those compiler tasks than the 5950X without providing any more performance; in fact, in the majority of the benchmarks I observed where the 12900k fails to win decisively (and/or loses), it is being pushed to its limits. In the benchmarks that it wins, it sits pretty comfortably below 90W. It's almost as though utilizing all of the CPUs resources at once kills its performance relative to the competition's product from over a year ago.

edit: and I'm not necessarily just talking averages. Look at LAMMPs for example.

 

[Carfax83]

The whole e-core vs p-core architecture seems misplaced until Microsoft and other OS makers can schedule it properly. If the e-core had both an IPC advantage and a clock advantage at full power over p-cores it would make sense, but otherwise what is the point?

The point is to offload light processing to the efficiency cores and thus save power, and also have them assist the performance cores with heavy processing when necessary. The whole purpose of the efficiency cores is to increase performance per watt and performance per mm2 of die space.

 

[JoeRambo]

Point still stands, 12900k burns more power in those compiler tasks than the 5950X without providing any more performance;

News at eleven? Just like 5950 is beaten badly in both performance and efficiency in plenty of low threaded workloads @ Phoronix tests.
That's why taking averages, even better taking geo average to factor out outliers and making dozens of different workloads is best.
Thats what Phoronix does, and 12900K is frankly better on average, while using 1.4W more on average:





So things can only get better for Intel here with RPL. As long as marketing morons don't release overvolted 300W monster once again.

 

[Carfax83]

Point still stands, 12900k burns more power in those compiler tasks than the 5950X without providing any more performance; in fact, in the majority of the benchmarks I observed where the 12900k fails to win decisively (and/or loses), it is being pushed to its limits. In the benchmarks that it wins, it sits pretty comfortably below 90W. It's almost as though utilizing all of the CPUs resources at once kills its performance relative to the competition's product from over a year ago.

Yes but if you consider the context that the 12900K has half the amount of big cores that the 5950x has, it begins to look more impressive in my opinion. The efficiency cores aren't really picking up much of the slack in those workloads. The performance cores are bearing the majority of the grunt, and are probably around twice as fast as the efficiency cores in multithreaded workloads like code compiling when you factor SMT and clock speeds. So to close the gap with AMD's best, Intel had to clock the performance cores as high as possible which obviously dramatically increased power draw.

Also, you're forgetting the 12600K, which obliterates the 5600x and outperforms the 5800x when it comes to compiling. When there is more parity between Alder Lake and Zen 3 in terms of big cores, Alder Lake wallops Zen 3.

 

[DrMrLordX]

News at eleven? Just like 5950 is beaten badly in both performance and efficiency in plenty of low threaded workloads @ Phoronix tests.

I already said that. The 12900k has the dubious distinction of winning benchmarks when the majority of the CPU is not utilized. That's when it hits the highest turbo clocks on the Golden Cove cores: when Gracemont clusters are not utilized, and when not all of the Golden Cove cores are utilized to their fullest.

Look at what happens in the Embree benchmark. There's no way the 12900k should be losing that bench, but it gets massacred.

And weren't we discussing compiler performance? Why are we shifting the goalposts?

That's why taking averages, even better taking geo average to factor out outliers and making dozens of different workloads is best.

No it doesn't. It introduces a bunch of workloads as noise and confuses the actual performance difference between the CPUs. Most reviewers specifically don't use averages or geometric mean across multiple benches for that reason.

So things can only get better for Intel here with RPL.

I disagree, since Raptor Lake adds more e-cores, which do not seem to be helping as much as they were supposed to.

Yes but if you consider the context that the 12900K has half the amount of big cores that the 5950x has, it begins to look more impressive in my opinion.

And whose fault is that? Intel won't produce any consumer CPUs on 10ESF with more than 8 Golden Cove/Raptor Cove cores.

Also, you're forgetting the 12600K, which obliterates the 5600x and outperforms the 5800x when it comes to compiling.

Who said anything about that? Yes the 12600k and 12700k are positioned better overall than the 12900k relative to the competition from last year, but that also wasn't really the topic of discussion . . .

 

[biostud]

So things can only get better for Intel here with RPL. As long as marketing morons don't release overvolted 300W monster once again.

But still AMD is changing from 7/12nm to 5/6nm and it seems like they will use it to maximize performance @ 170W for the 12c/16c parts. So I don't think they will close the gap when it comes to performance /watt with RPL vs zen4.

 

[igor_kavinski]

I'm glad that I didn't have any real need to upgrade. I would only want to spend my money when there is a clear winner. Right now, AMD wins some benchmarks and Intel wins others (a lot more since a lot of workloads are not good candidates for multi-threading). I don't see the point of arguing between 5950X and 12900K. Both are high end CPUs that represent only a small fraction of x86 sales. Buy the one that accelerates your workloads the best, or is the most power efficient for your use case.

There is NO clear winner. You don't really lose in the short term going either way. Long term, you do lose if you can't wait till the end of the year when both Intel and AMD have another face-off with their best engineering efforts yet.

Bottom line: Want to end 2022 with the best CPU ever? Wait.

 

[biostud]

I'm glad that I didn't have any real need to upgrade. I would only want to spend my money when there is a clear winner. Right now, AMD wins some benchmarks and Intel wins others (a lot more since a lot of workloads are not good candidates for multi-threading). I don't see the point of arguing between 5950X and 12900K. Both are high end CPUs that represent only a small fraction of x86 sales. Buy the one that accelerates your workloads the best, or is the most power efficient for your use case.

There is NO clear winner. You don't really lose in the short term going either way. Long term, you do lose if you can't wait till the end of the year when both Intel and AMD have another face-off with their best engineering efforts yet.

Bottom line: Want to end 2022 with the best CPU ever? Wait.

There will always be a better CPU just around the corner. The main reason for me to wait is that AM4 is EOL, and hopefully AM5 and X670 will support zen6 so a CPU upgrade will be a viable solution when time comes. But if not then it is not the end of the world. I just don't see the same upgrade path for a Intel system.

 

[JoeRambo]

But still AMD is changing from 7/12nm to 5/6nm and it seems like they will use it to maximize performance @ 170W for the 12c/16c parts. So I don't think they will close the gap when it comes to performance /watt with RPL vs zen4.

They need those watts, cause competing with 24C (32-40 cores in several years) is no joke, they are going to get outnumbered and beaten by atom cores in most MT throughput tests. 16C of Z4 can fight 8GC+24C no better than 8GC could fight 24 gracemonts today.
What happens when Intel reigns in their marketing idiots, iterates on Atom core further, puts it on proper voltage plane? And what is most important, once marketing morons are out, they will clock Gracemonts where they are incredibly efficient like 3.3Ghz or so and efficiency of whole chip suddenly moves ahead big time.

The real problem for AMD seems to be GC core and how strong it is in ST. Scenario where they have to use 5 dies of 5/6nm silicon to fight a single ~240mm^2 chip is not optimal for them and they might choose to not show up in that fight by diverting cache dies to server market.
So far from leaks Z4 does not seem like has many changes. AVX512 + L2 cache to feed said FP units. Without stacked L3 and without AVX512 workloads IPC gains might be dissapointing and below 25% some here are touting.

 

[nicalandia]

What chips has the author created to lecture what intel has created lol ?

What have YOU done to take high ground and discredit Chips and Cheese? Are you Jim Keller sock account?

 

[igor_kavinski]

I'm really interested in how Zen 4 will tackle the latency increase of DDR5. If V-cache isn't standard on all their Zen 4 SKUs, this could become a real problem for them.

 

[Henry swagger]

What have YOU done to take high ground and discredit Chips and Cheese? Are you Jim Keller sock account?

Lol you hurt

 

[tamz_msc]

They need those watts, cause competing with 24C (32-40 cores in several years) is no joke, they are going to get outnumbered and beaten by atom cores in most MT throughput tests. 16C of Z4 can fight 8GC+24C no better than 8GC could fight 24 gracemonts today.
What happens when Intel reigns in their marketing idiots, iterates on Atom core further, puts it on proper voltage plane? And what is most important, once marketing morons are out, they will clock Gracemonts where they are incredibly efficient like 3.3Ghz or so and efficiency of whole chip suddenly moves ahead big time.

The real problem for AMD seems to be GC core and how strong it is in ST. Scenario where they have to use 5 dies of 5/6nm silicon to fight a single ~240mm^2 chip is not optimal for them and they might choose to not show up in that fight by diverting cache dies to server market.
So far from leaks Z4 does not seem like has many changes. AVX512 + L2 cache to feed said FP units. Without stacked L3 and without AVX512 workloads IPC gains might be dissapointing and below 25% some here are touting.

Zen 4 is supposed to go after the 'low-hanging fruits' that can be improved upon from Zen 3. Remember Zen 3 was a back-to-the-drawing-board design. The last time we had this situation was Zen 1 to Zen 2. Then we easily got +15% IPC. I don't see any reason why Zen 4 cannot bring at least a +15% improvement over Zen 3.

I agree with what you say regarding E-cores and how they are being used by Intel. Though I cannot but think that RC cores are uninteresting based on what the speculation about caching has indicated so far. Every time there has been a hyping up of cache hierarchies from the Intel camp, it has been a disappointment. Cue Skylake > Skylake-X, Sunny Cove > Willow Cove.

 

[eek2121]

They need those watts, cause competing with 24C (32-40 cores in several years) is no joke, they are going to get outnumbered and beaten by atom cores in most MT throughput tests. 16C of Z4 can fight 8GC+24C no better than 8GC could fight 24 gracemonts today.
What happens when Intel reigns in their marketing idiots, iterates on Atom core further, puts it on proper voltage plane? And what is most important, once marketing morons are out, they will clock Gracemonts where they are incredibly efficient like 3.3Ghz or so and efficiency of whole chip suddenly moves ahead big time.

The real problem for AMD seems to be GC core and how strong it is in ST. Scenario where they have to use 5 dies of 5/6nm silicon to fight a single ~240mm^2 chip is not optimal for them and they might choose to not show up in that fight by diverting cache dies to server market.
So far from leaks Z4 does not seem like has many changes. AVX512 + L2 cache to feed said FP units. Without stacked L3 and without AVX512 workloads IPC gains might be dissapointing and below 25% some here are touting.

Zen 4 is supposed to go after the 'low-hanging fruits' that can be improved upon from Zen 3. Remember Zen 3 was a back-to-the-drawing-board design. The last time we had this situation was Zen 1 to Zen 2. Then we easily got +15% IPC. I don't see any reason why Zen 4 cannot bring at least a +15% improvement over Zen 3.

I agree with what you say regarding E-cores and how they are being used by Intel. Though I cannot but think that RC cores are uninteresting based on what the speculation about caching has indicated so far. Every time there has been a hyping up of cache hierarchies from the Intel camp, it has been a disappointment. Cue Skylake > Skylake-X, Sunny Cove > Willow Cove.

Raptor Lake will be outclassed by AMD Zen 4. Unsure why people think that adding more cores will make a huge difference when power limits exist. AMD gets to take advantage of a new node. Rumors point to a greater than 20% increase in single core performance, and possibly even more. In addition, AMD may be increasing TDP on some SKUs up to 170W.

 

[Abwx]

They need those watts, cause competing with 24C (32-40 cores in several years) is no joke, they are going to get outnumbered and beaten by atom cores in most MT throughput tests. 16C of Z4 can fight 8GC+24C no better than 8GC could fight 24 gracemonts today.


The real problem for AMD seems to be GC core and how strong it is in ST. Scenario where they have to use 5 dies of 5/6nm silicon to fight a single ~240mm^2 chip is not optimal for them and they might choose to not show up in that fight by diverting cache dies to server market.
So far from leaks Z4 does not seem like has many changes. AVX512 + L2 cache to feed said FP units. Without stacked L3 and without AVX512 workloads IPC gains might be dissapointing and below 25% some here are touting.

You are forgetting that Zen 4 will have a process advantage and that RPL has to cut the P core dedicated power by 50W to feed 8 extra E cores, so this will provide better perf/Watt and perf but not to the extent of a smaller node.

If Zen 4 provide 20% IPC gain the reminder of 5nm perf/watt improvement can be used to run at 17% higher frequency and get 40% higher perf at same power than the 5950X, and with a TDP raised to 170W that will get them roughly 50% better MT perfs.