Question Intel Q2: 7 nm in bad shape

[Atari2600]

Intel may have finished up work on those designs years ago, but will they be viable in 3-4 years when they [hopefully] become mass produced?

Will the process they are manufactured on closely resemble the process they were designed for?

If they are mismatched, you can end up with a sub-optimal product.

 

[DrMrLordX]

If they are mismatched, you can end up with a sub-optimal product.

That's one of the things I'm wondering. Intel trying to soldier on with their own nodes for CPUs will be suicide, but trying to adapt chips like Sapphire Rapids, Granite Rapids, and Meteor Lake to . . . whatever other node they can produce/get their hands on may have ugly results. There aren't many examples of Intel designing CPUs for outside nodes that we can use for reference.

 

[Atari2600]

Even if they do soldier on with their own nodes - is the 10nm they are getting now the same as the 10nm they intended to get in 2015 or 2016 when designing the CPUs?

What about 7? Is it the same?

To take something very simple - if densities are different, then path lengths are different, thermal concentrations are different and that throws (at the very least) power budgets out of whack from intention.

 

[Spartak]

Intel has the palm and sunny cove uarchs completed years ago and another few improvements on them.
Sunny features 20% more instruction units while other things are improved even more.It will be easily 20% faster per clock than skylake in anything that benchmarking sites are focusing on.Clocks will very probably be quite a bit lower than commetlake thou.
Sunny is intel's 10nm second iteration it was supposed to come out 2017 (to counter ZEN1) but there was no need to so they didn't release it.

Sunny Cove - Microarchitectures - Intel - WikiChip

Sunny Cove (SNC), the successor to Palm Cove, is a high-performance 10 nm x86-64 core microarchitecture designed by Intel for an array of server and client products, including Ice Lake (Client), Ice Lake (Server), Lakefield, and the Nervana NNP-I. The microarchitecture was developed by Intel's...

en.wikichip.org

"Sunny Cove was originally unveiled by Intel at their 2018 architecture day. Intel originally intended for Sunny Cove to succeed Palm Cove in late 2017 which was intended to be the first 10 nm-based core and the proper successor to Skylake. "

Rocket lake is supposed to use the third iteration, willow cove, backported to 14nm to get the best of both worlds, more IPC and more clocks.

Intel Rocket Lake to use 14nm back-port of the Willow Cove core architecture

Recent leaks suggest that the ageing Skylake architecture won't last beyond 2020's Comet Lake

www.pcgamesn.com

I have a hard time believing Rocket Lake is based on "3rd gen" Willow Cove, as it's been designed for 10nm with mainly a cache redesign that are both lacking from what we know of Rocket Lake. The Geekbench results also point to a Sunny Cove "v0.5" so if anything Rocket Lake is that mythical Palm Cove I've heard nothing about, just 3 years late.

I guess Palm Cove is rebranded to Cypress Cove, probably to include gen12 graphics?

Golem.de: IT-News für Profis

I've stated from day one of the "Cove introduction" there would a)be a 14nm backport b) it will be based on Sunny Cove or earlier, not Willow Cove . Nobody around here believed that but I still think I'll be proven correct.

Skipping Cypress/Palm Cove has proven to be one of Intel's biggest ever blunders. Technical hurdles are one thing, but failing to properly respond to them is a whole other level of redacted-up that only reveals how utterly beyond belief intel manufacturing mis- and underinformed the design and marketing departments that decided on the product roadmap.


Profanity is not allowed in tech areas.

AT Mod Usandthem

 

[A///]

Will the process they are manufactured on closely resemble the process they were designed for?

If they are mismatched, you can end up with a sub-optimal product.

This is a very good rhetorical question to my rhetorical question. I had not previously even presented such a question towards others who have yet to... as they say, see the light. Cheers

 

[bigi]

For those who have trouble visualizing dimensions less than 1mm, please see this: https://htwins.net/scale2/

Once you get to 1 nano meter, it is easy to compare it to other objects. It might also help with understanding why continuous die shrinking gets more difficult.

 

[jpiniero]

For those who have trouble visualizing dimensions less than 1mm, please see this: https://htwins.net/scale2/

Once you get to 1 nano meter, it is easy to compare it to other objects. It might also help with understanding why continuous die shrinking gets more difficult.

They aren't really physically shrinking the transistor that much. The density gains are mainly coming from going "3D" than anything else.

 

[DrMrLordX]

Even if they do soldier on with their own nodes - is the 10nm they are getting now the same as the 10nm they intended to get in 2015 or 2016 when designing the CPUs?

We know that 10nm is changed significantly from what they tried to use in 2017 with CannonLake. We also know they've managed to produce Sunny and Willow Cove on 10nm, albeit with poor yields. The yields may still be abysmal. Intel isn't really saying, but the Tiger Lake delays are worrisome, as are the IceLake-SP delays.

What about 7? Is it the same?

All we know officially is that it's delayed "6-12 months" and that Murthy got wiped out over it.

To take something very simple - if densities are different, then path lengths are different, thermal concentrations are different and that throws (at the very least) power budgets out of whack from intention.

That might explain why IceLake-U has such poor power characteristics near its peak boost clocks. TigeLake-U looks stronger in that clockrange though, maybe. It isn't clear if functional yields are better though, or if they just redid Willow Cove to work better on 10nm+/++/whateveritisthey'reusingnow

 

[LightningZ71]

Is it possible that, while Ice Lake-U was largely a "straight port" (as much as that is possible going from the original 10nm target to the relaxed one that they are currently using), Tiger Lake U is an "optimized port" that has had a "re-layout" of sorts to address all those little things that come up when the design rules for a process are changed? Largely what DrMrLordX said, but said differently I guess.

 

[Ajay]

I have a hard time believing Rocket Lake is based on "3rd gen" Willow Cove, as it's been designed for 10nm with mainly a cache redesign that are both lacking from what we know of Rocket Lake. The Geekbench results also point to a Sunny Cove "v0.5" so if anything Rocket Lake is that mythical Palm Cove I've heard nothing about, just 3 years late.

I guess Palm Cove is rebranded to Cypress Cove, probably to include gen12 graphics?

Golem.de: IT-News für Profis

I've stated from day one of the "Cove introduction" there would a)be a 14nm backport b) it will be based on Sunny Cove or earlier, not Willow Cove . Nobody around here believed that but I still think I'll be proven correct.

Skipping Cypress/Palm Cove has proven to be one of Intel's biggest ever blunders. Technical hurdles are one thing, but failing to properly respond to them is a whole other level of redacted-up that only reveals how utterly beyond belief intel manufacturing mis- and underinformed the design and marketing departments that decided on the product roadmap.

Pretty sure marketing guess a pass on this one. All the problems seem to be technical (/management related). If Cypress Cove yields 10% more PPC and RKL, with max of 8 cores) can run TVB pretty much at the same level of CML, then I think Intel will be happy with that. At this point, it's pretty clear that Intel doesn't care about power consumption for it's top enthusiast CPUs. Kinda surprised that something closer to Sunny Cove wasn't possible - seems like that design has been around long enough to backport.

 

[naukkis]

Kinda surprised that something closer to Sunny Cove wasn't possible - seems like that design has been around long enough to backport.

That's because when you shrink process you got more transistors in same area to be used to make faster arch to be able to clock as high as design with less transistors in previous process.. That just won't work backwards.

 

[Ajay]

That's because when you shrink process you got more transistors in same area to be used to make faster arch to be able to clock as high as design with less transistors in previous process.. That just won't work backwards.

It can, with caveats. Density can be reduced, on purpose, reduce hot spots (though that can increase parasitic capacitance) at the cost of larger die sizes (hence, 8 core max). Top clocked examples can be binned (as with CML) to use the best quality silicon for the most expensive CPUs. Some of the performance gains from Sunny Cove can be left off to reduce die size. It's all about tradeoffs and, clearly, you don't get something for nothing. Anyway, if what @Spartak said is true, I'm just a bit surprised that Intel didn't shoot higher - maybe there just wasn't enough design/sim time available to hit the prospective TTM.

 

[naukkis]

It can, with caveats. Density can be reduced, on purpose, reduce hot spots (though that can increase parasitic capacitance) at the cost of larger die sizes (hence, 8 core max). Top clocked examples can be binned (as with CML) to use the best quality silicon for the most expensive CPUs. Some of the performance gains from Sunny Cove can be left off to reduce die size. It's all about tradeoffs and, clearly, you don't get something for nothing. Anyway, if what @Spartak said is true, I'm just a bit surprised that Intel didn't shoot higher - maybe there just wasn't enough design/sim time available to hit the prospective TTM.

Nope. Transistors firing every clock cycle makes those hot spots and those can be layered to be more relaxed, but for data arrays like caches, reorder buffers, register files and so on there's a limit how big those arrays can be for signals to be able to travel in one clock cycle. Of course pipeline stages can be added for larger structures but it won't be same core anymore.

History knows many cpu cores that were too big and clocked lowly - and failed.

 

[Doug S]

For those who have trouble visualizing dimensions less than 1mm, please see this: https://htwins.net/scale2/

Once you get to 1 nano meter, it is easy to compare it to other objects. It might also help with understanding why continuous die shrinking gets more difficult.

Nothing in a "7nm" process is actually 7nm in size. The process names became disconnected from physical dimensions of the transistor many years ago.

In the past if you wanted to double the number of transistors that could fit into a given area you'd shrink physical dimensions by sqrt(2) and presto! That's why the process sizes/names were always following that sqrt(2) naming. As the form of transistors changed the physical dimensions stopped shrinking by sqrt(2) in each new process but we were still able to double the transistors per area.

After that the process names continued "shrinking" by sqrt(2) since not everyone made the same changes to transistors at the same time. More to the point though, the names actually came from an international organization (ITRS) that formulated a roadmap intended to help everyone in the industry from the ones making the fab tools, to the ones making the design software, to the ones doing packaging etc. know what was coming and when. I don't think it exists anymore, since the industry has consolidated so much it isn't so necessary these days.

The last couple of generations TSMC is only increasing the number of transistors per area by around 70%, but is still naming their processes via the sqrt(2) method. So I guess if you consider N7 to be "7nm" then N3 really should be called "4nm" but it really doesn't matter (and this may be why TSMC quit naming their processes by size but now calls them N7, N5 etc.) The point is that TSMC's N3 / 3nm process is not going to have anything with a width of only 3nm so the atomic limits aren't going to come into play as soon as the process names and sizes of atoms would appear to suggest.

We may never hit the physical limits - I think most people in the industry agree that we will hit economic limits before we hit physical limits. Developing and deploying a smaller process keeps getting more expensive every generation. At some point, developing and deploying a new process will not make very much money, and all signs will point to the next generation being a money loser. That's where we'll stop, until someone finds a better way to make such tiny structures. Something even better and faster at drawing very fine lines than EUV, or perhaps a way to efficiently build things "from the bottom up" rather than our current "top down" strategy.

 

[traderjay]

Why would they even put murthy in charge of process and manufacturing in the first place when he doesn't even have the relevant experience? Qualcomm is fabless...it will make far more sense if the person comes from ASML or Lam Research and the likes.

 

[Saylick]

Why would they even put murthy in charge of process and manufacturing in the first place when he doesn't even have the relevant experience? Qualcomm is fabless...it will make far more sense if the person comes from ASML or Lam Research and the likes.

Same can be said of putting in Bob Swan, the former CFO, in charge of Intel, an engineering company. An engineer or someone on the fab side of things would have made more sense I think. Bob was originally the interim CEO but then became permanent CEO, so I think people on the inside probably didn't want to be the fall guy so not one stepped up, forcing the Board to nominate Bob for the permanent role.

 

[jpiniero]

Same can be said of putting in Bob Swan, the former CFO, in charge of Intel, an engineering company. An engineer or someone on the fab side of things would have made more sense I think.

Like BK? Heh.

 

[traderjay]

Same can be said of putting in Bob Swan, the former CFO, in charge of Intel, an engineering company. An engineer or someone on the fab side of things would have made more sense I think. Bob was originally the interim CEO but then became permanent CEO, so I think people on the inside probably didn't want to be the fall guy so not one stepped up, forcing the Board to nominate Bob for the permanent role.

The thing is a CEO doesn't need to be fully technical because he relies and delegates duties and responsibilities to other leaders in the org. Its different when you run process and manufacturing and doesn't have any prior background in that area like Murthy.

 

[Saylick]

Like BK? Heh.

All jokes aside, from a purely merit-based point of view, I do think BK understands the role better than Bob Swan, given his background in the fab side of the business.

The thing is a CEO doesn't need to be fully technical because he relies and delegates duties and responsibilities to other leaders in the org. Its different when you run process and manufacturing and doesn't have any prior background in that area like Murthy.

That's a fair point in that the CEO usually ends up delegating work to other leaders in the org, but I still think a former CFO in the role just isn't the right fit for a company like Intel. Now, I am aware that there are other success stories of former CFOs heading large tech companies (*ahem Apple) but I don't think they are as engineering dependent as Intel is.

Bob doesn't have an engineering background whatsoever, so I think he can only take in information from his technical delegates at face value at best. If his head of fab says they will need an extra year to develop their 7nm node, I don't think Bob has the background to delve deeper into why that's happening beyond just asking his head of fab guy what the issue is. He'll just have to accept what his fab guy tells him and say, "Okay, if you say so. Just keep me updated" but ultimately be none the wiser.

Conversely, if you look at AMD with Dr. Su as CEO, she can directly weigh-in on major engineering decisions because she has that background (both semiconductor design and fab experience) to know if something passes the smell test.

Guys like Bob, and technically Tim Cook at Apple, are good at optimizing the financials or operations of a company (i.e. milking a cash cow for all its worth, trimming down on fat). If the company is already successful and well past the growth phase, bean counter CEOs are ideal because they can really help improve the EPS of the company. However, if there are immediate threats to the company and a long-term vision is required, good luck trying to turn a cruise liner around when the head honcho doesn't have the background to intuit which direction they need to point the ship. Bean counter CEO might point the company into doubling down on their most profitable line of business, which might squander the company in the long term if that line of business is dying, while visionary CEO might divert resources into developing and/or diversifying the company's portfolio instead.

 

[traderjay]

All jokes aside, from a purely merit-based point of view, I do think BK understands the role better than Bob Swan, given his background in the fab side of the business.


That's a fair point in that the CEO usually ends up delegating work to other leaders in the org, but I still think a former CFO in the role just isn't the right fit for a company like Intel. Now, I am aware that there are other success stories of former CFOs heading large tech companies (*ahem Apple) but I don't think they are as engineering dependent as Intel is.

Bob doesn't have an engineering background whatsoever, so I think he can only take in information from his technical delegates at face value at best. If his head of fab says they will need an extra year to develop their 7nm node, I don't think Bob has the background to delve deeper into why that's happening beyond just asking his head of fab guy what the issue is. He'll just have to accept what his fab guy tells him and say, "Okay, if you say so. Just keep me updated" but ultimately be none the wiser.

Conversely, if you look at AMD with Dr. Su as CEO, she can directly weigh-in on major engineering decisions because she has that background (both semiconductor design and fab experience) to know if something passes the smell test.

Guys like Bob, and technically Tim Cook at Apple, are good at optimizing the financials or operations of a company (i.e. milking a cash cow for all its worth, trimming down on fat). If the company is already successful and well past the growth phase, bean counter CEOs are ideal because they can really help improve the EPS of the company. However, if there are immediate threats to the company and a long-term vision is required, good luck trying to turn a cruise liner around when the head honcho doesn't have the background to intuit which direction they need to point the ship. Bean counter CEO might point the company into doubling down on their most profitable line of business, which might squander the company in the long term if that line of business is dying, while visionary CEO might divert resources into developing and/or diversifying the company's portfolio instead.

Well said! The Intel CEO case is an oddity since nobody wants the permanent role so they have to stick somebody in there. Rory read, the former AMD CEO is another example of non-technical CEO but he knows when to leave and pass on the torch to an industry veteran. But what we are saying here is the Murthy guy leading the process and manufacturing. I guess Intel's reputation is making rounds in the industry and no real talent wants to stay there for long.

 

[Doug S]

That's a fair point in that the CEO usually ends up delegating work to other leaders in the org, but I still think a former CFO in the role just isn't the right fit for a company like Intel. Now, I am aware that there are other success stories of former CFOs heading large tech companies (*ahem Apple) but I don't think they are as engineering dependent as Intel is.

Tim Cook is a former COO, not CFO. The COO is in charge of operations, not finance. Things like securing supply deals, managing inventory levels, etc.

 

[Saylick]

Tim Cook is a former COO, not CFO. The COO is in charge of operations, not finance. Things like securing supply deals, managing inventory levels, etc.

Oh, you're right. My mistake then.

 

[Ajay]

Nope. Transistors firing every clock cycle makes those hot spots and those can be layered to be more relaxed, but for data arrays like caches, reorder buffers, register files and so on there's a limit how big those arrays can be for signals to be able to travel in one clock cycle. Of course pipeline stages can be added for larger structures but it won't be same core anymore.

History knows many cpu cores that were too big and clocked lowly - and failed.

It's xtors switching per clock per unit area. I'm modern CPUs we have clock gating and multiple voltage and timing domains to improve efficiency, allow higher clock speeds and prevent clock skew. I'm not talking about giant sized chips here, just slightly larger. Don't care about history. Intel 14nm is probably one of the best characterized processes in history - given it's long use.

 

[Zucker2k]

Francois Piednoel on how to fix Intel....

 

[DrMrLordX]

But who will fix Francois?