- Jul 8, 2008
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Intel's Open-Source Technology Center pushed some changes towards the kernel. From these patches Larabel has compiled following information:
ULT, ULX and DT are self-explanatory. But what about Halo? How would a Halo GT1 differ from DT GT1? SRV is presumably reserved for the small-socket Xeons? WKS is a weird one.
Bit crazy how many variant of iGPU they will have, when combined with different CPUs will result in large number of SKU. SKU inflation and segmentation continues unabated at Intel.
Another thing that stood out:
You can read the entire article at Phoronix.
Phoronix said:The initially added Skylake PCI IDs / product support come in several groups and include:
Skylake ULT GT1: 0x1906
Skylake ULT GT2: 0x1916
Skylake ULT GT2F: 0x1921
Skylake ULT GT3: 0x1926
Skylake ULX GT1: 0x190E
Skylake ULX GT2: 0x191E
Skylake DT GT1: 0x1902
Skylake DT GT2: 0x1912
Skylake Halo GT1: 0x190B
Skylake Halo GT2: 0x191B
Skylake Halo GT3: 0x192B
Skylake SRV GT1: 0x190A
Skylake SRV GT2: 0x191A
Skylake SRV GT3: 0x192A
Skylake WKS GT2: 0x191D
ULT, ULX and DT are self-explanatory. But what about Halo? How would a Halo GT1 differ from DT GT1? SRV is presumably reserved for the small-socket Xeons? WKS is a weird one.
Bit crazy how many variant of iGPU they will have, when combined with different CPUs will result in large number of SKU. SKU inflation and segmentation continues unabated at Intel.
Another thing that stood out:
Yes, at last! I hope motherboard manufacturers give us at least one decent motherboard with three DP or HDMI outputs.Phoronix said:The HD Graphics Gen9 for SKL/Skylake has a third display plane compared to Haswell/Broadwell and features five HDMI/DP/eDP display ports.
You can read the entire article at Phoronix.