• We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.

Discussion Intel Nova Lake in H2-2026: Discussion Threads

T

Tigerick

Senior member
01-Process.jpg
With Pat pretty much confirm the existence of Nova Lake; let's started new thread about Nova Lake, the successor of Arrow Lake.

01-Process.jpg

Even though Nova Lake is still two years away (currently target for Q4 2026 release), my source has provided more information below:
​
  • Once again, Intel will change the tile methodology of Nova Lake. The IMC no longer inside CPU tile, it is going to be integrated inside SoC tile. Update: GPU tile is another die connecting to SoC.
  • Higher NGU (new term for NoC of SoC tile) and ring clocks should fix the memory latency issues, we shall see.
  • The top-end SKU of NVL-SK / S / HX will integrate V-cache similar to AMD's X3D. My source can't confirm the amount of L3 cache but the recent leaks about 144MB seems valid.
  • Currently, NVL platform will support up to 128-bit DDR5-8000 (bump up to DDR5-8800), the same memory speed AMD would support for upcoming Zen6.
  • Both Intel's NVL and AMD's Zen6 are targeting for Q4-2026 release.
  • As for process node, well Intel will definitely try to use IFS but as Pat said there are going to have some tiles that are made by TSMC, we should hear more in the future.

Preliminary Leaks of Intel Nova Lake and Zen6 Lineup

Nova Lake - SCPU TilesCPU Cores4 LPe StandardTDPL3 CachebLLC 144MB per dieZen 6CPU TilesCPU Cores2 LPe + SMTL3 CacheX3D 96MB ?
Core Ultra 9N2 x 216 + 3248 T150 W72 MB288 MBRyzen 92 CCDs2448 T96 MB192 MB
14 + 2442 T150 W2040 T
Core Ultra 712 + 2436 T150 W1632 T
Core Ultra 5N2 x 18 + 1624 T125 W36 MB144 MBRyzen 71 CCD1224 T48 MB144 MB
8 + 1220 T125 W1020 T
6 + 814 T125 W
Ryzen 51 CCD816 T
Core Ultra 3N2 x 14 + 812 T65 W18 MB612 T
18A x 14 + 04 T





Mobile Nova Lake and Panther Lake Tile Design

Nova LakeNodePanther LakeNode
CPU8 + 16N24 + 8 + 4, SoC, NPU5, IMC18-A
SoC4 LPe, IMC, NPU618-A
GPU12 Xe3 Battlemage CoreN3E12 Xe3 Battlemage CoreN3E
4 Xe3 Battlemage CoreI34 Xe3 Battlemage CoreI3
PCD (IOD)IODI3IODN6





Preliminary Mobile Nova Lake & Panther Lake Lineup

TSMC N2CPU (4 LPe Standard)GPU TileNPU6Intel 18ACPU (4 LPe Standard)GPU TileNPU5
NVL-HX8 + 164 Xe Core (Intel 3)80 TOPSPanther Lake X4 + 812 Xe Core (N3E)50 TOPS
NVL-X ?4 + 812 Xe Core (N3E)80 TOPSPanther Lake - H4 + 84 Xe Core (Intel 3)50 TOPS
Wildcat Lake - U2 + 0Integrated 2 Xe Core18 TOPS




Bonus: AMD's Zen6
Beside higher core count, Zen6 is still targeting for Q4-2026's release; same timings as NVL.

Zen6's CCD will be fabbed by N3 family, most likely N3P/X?



That's all I know atm, enough to start the discussion about upcoming Intel's Nova Lake.
 
Last edited:
While I understand Zen6 will be limited to 128b DDR interface due to promised AM5 support, it makes no sense for Intel to significantly increase the core count and stick to 128b DDR inteface. Especially since nobody expects mobo backwards compatbility from them.
 
I wonder if Nova Lake will still use the ring bus or if they're updating it or maybe even ditching it entirely. The ring bus seems like it's one of Intel's weakest points. It's already bad with 12 stops and it's only going to get worse if they increase the core count.

AFAIK Intel is the only company that has anything like a ring bus. The way it works is each p-core (or 4 e-cores) gets a stop on the bus with an equal share of the L3 cache. When a core needs data in another core's L3, the data has to "hop" from stop to stop. Anandtech's Raptor Lake core-to-core latency charts show that the latency can vary depending on how many hops it has to take. In comparison, Zen4's core-to-core latency within a CCX is basically the same no matter which cores it's going between (with the exception of SMT threads). Core-to-core latency isn't super important for performance, but this shows how the cache hierarchy of the ring bus has some fundamental downsides with large core counts.

The AIDA latency of the 285k, 14900k, 14600k, and 9700x shows how bad the latency on Intel is. For memory latency, Zen5 matches Raptor Lake's memory latency even though Ryzen uses chiplets.

In my opinion the sooner they switch away from it the better.
 
The Nova Lake and Diamond Rapids CPUID were recently released: 13_00H, 13_01H. Not that it is important information, but maybe it'll help identify leaks later.
See table 1-1:

"Updated Table 1-1, “CPUID Signature Values of DisplayFamily_DisplayModel,” to add values for future processors supporting Nova Lake performance hybrid architecture and future processors based on Diamond Rapids microarchitecture."
 
Last edited:
What other topology is possible than rings? I thought AMD also used a ring-like traffic when it moved onto 8-core CCX.
 
I always figured they would move to a mesh eventually as they already developed one for the higher core count CPU's.
 
After digging deeper, I found that Zen3 does use a ring bus of sorts. So I was wrong about that. I still stand by my main point that Intel's ring bus is bad.
Now with eight cores per CCX, since launch, AMD has been extremely coy about telling anyone publicly how those cores are connected together. When asked at launch if the cores in a Zen 3 eight-core CCX were fully connected, AMD’s general attitude was ‘Not quite, but close enough’. This would mean something between a ring and something between an all-to-all design, but more verging on the latter.

...

In our testing, our results show that while AMD’s core complex is not an all-to-all connection, it also doesn’t match what we would expect from ring latencies. Simply put, it’s got to be more than a ring. AMD has been very coy on the exact details of their CCX interconnect – by providing a slide saying it’s a ring reinforces the fact that it’s not an all-to-all interconnect, but we’re pretty sure it’s some form of a bisected ring, a detail that AMD has decided to leave out of the presentation.
Click to expand...

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
www.anandtech.com
 
Thanks to old member @Exist50 providing leaks about NVL in Reddit. Also, Intel pretty much confirmed that compute tile of NVL going to be dual source, ie TSMC and IFS.

And I believe in what @Exist50 leaks. The top compute die of NVL going to have 8+16 cores which will be fabbed by TSMC's N2P process. (I am expecting N2 not N2P due to HVM timings). Another 4+8+4 die will be fabbed by IFS's 18A....

And here comes the super duper configuration: 2 dies of 8+16 will become 16+32 of NVL-SK. NVL-HX / S comes with 1 die of 8+16. With AMD's Zen6 rumored to come with 24 P-core, Intel will response with 16+32 NVL-SK model.

Now we know 18A is not up to TSMC's N2 standard. I hope nobody in this forum should believe in Intel fancy marketing term. At the end of the day, PPAC matters, and Intel has been tweaking the words / BS to fool people.

NVL.jpg
 
Last edited:
money.udn.com

台積電2奈米 英特爾下單 法人看好下半年業績熱轉 | 產業熱點 | 產業 | 經濟日報

台積電規劃下半年量產2奈米製程，近期相關客戶陸續浮上檯面，繼超微宣布下單台積電2奈米後，市場傳出，英特爾也加入台積電2奈...
money.udn.com money.udn.com

After AMD officially pre-announced they are among the first to fab N2 SoC, namely Venice with 32-core Zen6 (Server SoC), Taiwan paper has mentioned that Intel going to use N2 process to make client SoC, likely refer to Nova Lake's compute tile with 8+16 cores.

Yep, once again IFS failed to mass produce the compute tile in 18A process, so much for leadership, myASS...😎
 
Tigerick said:
money.udn.com

台積電2奈米 英特爾下單 法人看好下半年業績熱轉 | 產業熱點 | 產業 | 經濟日報

台積電規劃下半年量產2奈米製程，近期相關客戶陸續浮上檯面，繼超微宣布下單台積電2奈米後，市場傳出，英特爾也加入台積電2奈...
money.udn.com money.udn.com

After AMD officially pre-announced they are among the first to fab N2 SoC, namely Venice with 32-core Zen6 (Server SoC), Taiwan paper has mentioned that Intel going to use N2 process to make client SoC, likely refer to Nova Lake's compute tile with 8+16 cores.

Yep, once again IFS failed to mass produce the compute tile in 18A process, so much for leadership, myASS...😎
Click to expand...

Saying they're using N2 doesn't mean they're using it for everything. Intel's 18A capacity is going to be limited, and Intel might not even get all of it if they have customers taking a good sized chunk of it.
 
Doug S said:
Saying they're using N2 doesn't mean they're using it for everything. Intel's 18A capacity is going to be limited, and Intel might not even get all of it if they have customers taking a good sized chunk of it.
Click to expand...
Yeah, that’s my understanding.

Basically, there’s not enough 18A capacity if they used it purely for themselves and they want to reserve capacity for potential IFS customers. The only way this works is because TSMC let’s them be a customer, ironically.
 
Likely the last time I buy Intel. Just bought nifty new 1851 mobo and 265k. Stupid me thinking i had a gen or two if cpu upgrades. I cant trust Intel anymore. Regardless of reasoning, you dont release a SINGLE gen chipset and socket. I truly feel taken for a ride. AMD will be next for me likely.
 
igor_kavinski said:
There is a rumor that the 300 series will be LGA1851 compatible because Nova Lake is still pretty far away. I guess we find out by December of this year.
Click to expand...
Well that would be great. At least I would get 1 gen of an upgrade. But I have doubts now. Look at AM5. How many gens can it utilize? Folks who purchased AM5 got more than their moneys worth. Like you say. We'll see.
 
Last edited:
Boosting clocks is only going to help Cinememe benchmarks, it won't do much for gaming since the memory latency is so high. They need DDR5-12000 before the arch is even competitive with Raptor Lake...
 
Keysplayr said:
Likely the last time I buy Intel. Just bought nifty new 1851 mobo and 265k. Stupid me thinking i had a gen or two if cpu upgrades. I cant trust Intel anymore. Regardless of reasoning, you dont release a SINGLE gen chipset and socket. I truly feel taken for a ride. AMD will be next for me likely.
Click to expand...

That's been Intel's MO forever. Support two CPU's per socket. Only recently three with "Raptor Lake Refresh" which doesn't really count. Compare that to AM2 or AM4.

alcoholbob said:
Boosting clocks is only going to help Cinememe benchmarks, it won't do much for gaming since the memory latency is so high. They need DDR5-12000 before the arch is even competitive with Raptor Lake...
Click to expand...

Did everyone adopt "Cinememe" from Adroc?
 
igor_kavinski said:
There is a rumor that the 300 series will be LGA1851 compatible because Nova Lake is still pretty far away. I guess we find out by December of this year.
Click to expand...

If anything, I would assume that Bartlett Lake will be LGA 1700.

A minor refresh of Arrow on desktop could very well happen.
 
Keysplayr said:
Likely the last time I buy Intel. Just bought nifty new 1851 mobo and 265k. Stupid me thinking i had a gen or two if cpu upgrades. I cant trust Intel anymore. Regardless of reasoning, you dont release a SINGLE gen chipset and socket. I truly feel taken for a ride. AMD will be next for me likely.
Click to expand...
This will be same if you buy Zen 6 in 2026 if anything NVL will be better for a new socket but yeah it sucks to buy a Mobo for single gen use if you upgrade too much.
 
You must log in or register to reply here.

TRENDING THREADS

Back
Top