Intel Nehalem

[Nemesis 1]

Since we pretty much know Penryn is going to have between a 10 to 20% increase in performance over Merom . I am including what ever advantage X38 chipset.

I wanted to ask you guys what you think nehalems performance advantage will bring. Since K10 has been talked about since June of 06 its reasonable to discuss Nehalem now since were closer to its launch now than we were to K10's launch when discussion began about it.

I am most interested in In the SHARED L1 cache that will be on the nehalem which in its self should bring a sizeable performance boost over Penryn .

Than of course there is . Hyper threading on Nehalem and statements by Intel that it will be completely differant from P4 HT. To me that means multi core working together on 1 thread. We know Intel has been working on Mitosis for along time so Ifeel this is what HT on Nehalem will be . Aside from multicore being able to work on a single thread it will also have the ability to work on multi threads. 4 cores 8 threads.

Than there is Ondie memory controler which to me is no big deal Since I am not interested in servers. But CSI on all Nehalem processors with or without ondie memory controller is most interesting and should bring some interesting performance gains considering it with operate @ 5ghz+ in both directions.

So many believe that Nehalem will bring about a 20 - 30% performance Improvement over penryn . IF Nehalem HT infact does also work multi core on single thread . the improvements should be higher than 50% over Penryn . That is a big if.

Than in 09 when Intel goes to 32nm . Intel has stated many times that 3D gates will be on this process. Just as they said highK and metal gates on the 45nm process. 3D gates on nehalem should bring another 10-20% performance increase over metal gates. of course 3D gates will likely also be metal gates also.

It seems to me Intel has all its Ducks lined up and is exacuting flawlessly.

So if everthing other than the HT (mitosis) thing appears on Nehalem . Even without . Any other improvements to the core logic which we know there will be more improvements. Intels nehalem should be 50% better than penryn at the same clock. When we see Nehalem C in 09.

Weather(climate change) you like intel or not . These guys are setting standards now at a rate thats simply without a doubt very impressive.

I don't go out and buy the next best thing every time it appears . But its going to be very hard for me not to jump all over Nehalem when its released . But I won't as I will not leave the penryn untel nehalem C is released. But I do have an advantage as my wife and myself are on differant up grade cycles. Which works out great for us. Thats the best thing I ever got from the forums. When I read that some couples were on differant upgrade cycles. It makes sense and it works . Thanks to those who pointed us in that direction . It works and its very smart.

 

[Keysplayr]

I read somewhere that not all versions of Nehalem CPU's will have an Integrated Memory Controller, but all of them will STILL utilize a Northbridge and a Southbridge (two chipset solution as always has been) but with the chipset having different "responsibilities". Apparently Intel must be taking baby steps toward a IMC solution IF that is where they feel the best performance lies. They may be on another road (a different road from AMD when it comes to FSB/IMC).

If anyone was to say what percentage Nehalem would be faster than say Penryn, it would only be grabbing a number out of thin air. Unless somebody has inside info and breaks NDA, we won't know squat. IMHO.

 

[bryanW1995]

I had a dream last night that I got the inside scoop on nehalem. I woke up just before signing the nda, fortunately, so I can share my secret info with you all. For a price.

 

[Idontcare]

Originally posted by: Nemesis 1
Than of course there is . Hyper threading on Nehalem and statements by Intel that it will be completely differant from P4 HT. To me that means multi core working together on 1 thread. We know Intel has been working on Mitosis for along time so Ifeel this is what HT on Nehalem will be .

Than in 09 when Intel goes to 32nm . Intel has stated many times that 3D gates will be on this process. Just as they said highK and metal gates on the 45nm process. 3D gates on nehalem should bring another 10-20% performance increase over metal gates. of course 3D gates will likely also be metal gates also.

Two things about my background make me qualified to comment on this - (1) I built and used parallel computing systems (Beowulfs) so am quite familiar with Amdah'ls law, and (2) was a process development engineer at TI for 10+ years and worked on 32nm development before I left the company.

Having said that - regarding the comment of one thread being processed by two or more cores....there is no logical (as in 0's and 1's) way to explicitely do one thing by having two things attempt to work on it if that one thing cannot be converted into two things. I.e. the only way a single-thread could be processed by two or more cores is if the single-thread really had intrinsic multi-thread characteristics but for whatever reason the single-thread was not coded as a multi-thread.

So you can hardware reverse compile the thread and force parts of it (albeit with substantial processing overhead in its own right, recompiling on the fly as it were) to be multi-threaded but this merely accomplishes what could have been done with a rewrite/recompile of the source to take advantage of multi-threads in the first place.

In other words your older software from the pre-multicore days can be pseudo-multicored. This is logically possible. But a thread which is inherently a single-thread because it is truly a sequential instruction thread with zero parallelizations simply can never be parallelized.

You can do smoke/mirror things with latencies and parallel speculative processing relating to the single-thread, but you simple cannot make 1 instruction = 0.5 instruction + 0.5 instruction and claim you have put two cores to work.

There is no "but the guru's could do it, hypothetically, blah blah". It doesn't work that way. Amdahl and company were superbly intelligent folks in the 60's, they did not simply overlook the logic of the math here.

Second, regarding 32nm and 3-D gates, Intel would not implement HK/MG as a one-node solution. If you know anything about process development and technology nodes then I should not have to say anything more. 3-D gates will have already been assessed and deemed not necessary until at least the 22nm node...the proof of which is contained in the fact that 45nm is planar CMOS with HK/MG xtors.

If 45nm = planar CMOS with HK/MG (1st node introduction) then 32nm = planar CMOS with HK/MG (2nd node introduction).

22nm would be the first opportunity that Intel would take to introduce anything significantly new into the xtor...3D gates would qualify as something significantly new.

 

[Nemesis 1]

Originally posted by: keysplayr2003
I read somewhere that not all versions of Nehalem CPU's will have an Integrated Memory Controller, but all of them will STILL utilize a Northbridge and a Southbridge (two chipset solution as always has been) but with the chipset having different "responsibilities". Apparently Intel must be taking baby steps toward a IMC solution IF that is where they feel the best performance lies. They may be on another road (a different road from AMD when it comes to FSB/IMC).

If anyone was to say what percentage Nehalem would be faster than say Penryn, it would only be grabbing a number out of thin air. Unless somebody has inside info and breaks NDA, we won't know squat. IMHO.

Couldn't agree more. Intel has said however that nehalem with or without IMC will have CSI . CSI is running at 5+ ghz both directions. This in its self will added a noticeable increase in north and southbridge performance.
Just the fact that it includes HT no matter how it works has to be included as a performance gain . I think we can all agree on that . Since I am sure and most all would agree that intel will also include substancial improvements to the core logic . It is not unreasonable to expect at least a 30% performance increase in performance at same clock. As has been stated so many times that Intel C2D rarely takes advantage of the fact its a 4 issue core. Its easy to see that nehalem will take advantage of a 4 issue core. On the 45nm process.

The really great part about speculating on Nehalem is the fact that Intel fall IDF is coming up shortly. At this time we will be snowed under with Penryn performance numbers and demo's . At the same time intel will release a large amount of info on Nehalem . So in a very short time we will all know so much more .

This makes it very fun to speculate now. So that when we recieve more info on Nehalem at the fall IDF. Than we can see which people have very good insight as to nehalem will be.

I suspect the biggest piece of info that will be released as there are hints of it now. That will get the fan-boys attention on both sides in an uproar will be Nehalem with larabee on die.

Its a very exciting time in the forums now . With Intel hitting us with something new and better once a year. It makes the cpu section of the forums so much more entertaining . Wouldn't you agree?

 

[Keysplayr]

Yup, I agree. Very interesting times with this "change" within Intel. It's like they've been "reborn" and are sticking to it. It does make the CPU forums a lot more interesting these days. And despite some folks saying that speculation is a waste of time, I disagree, it's fun and interesting to talk about what "could be". Nehalem being 30% faster clock per clock over Penryn, is certainly not a stretch of the imagination. I believe it is actually a given. But as you said, lets see what IDF has to offer this year. Lets see what Intel will let slip out.

Keys

 

[Nemesis 1]

Originally posted by: Idontcare

Originally posted by: Nemesis 1
Than of course there is . Hyper threading on Nehalem and statements by Intel that it will be completely differant from P4 HT. To me that means multi core working together on 1 thread. We know Intel has been working on Mitosis for along time so Ifeel this is what HT on Nehalem will be .

Than in 09 when Intel goes to 32nm . Intel has stated many times that 3D gates will be on this process. Just as they said highK and metal gates on the 45nm process. 3D gates on nehalem should bring another 10-20% performance increase over metal gates. of course 3D gates will likely also be metal gates also.

Two things about my background make me qualified to comment on this - (1) I built and used parallel computing systems (Beowulfs) so am quite familiar with Amdah'ls law, and (2) was a process development engineer at TI for 10+ years and worked on 32nm development before I left the company.

Having said that - regarding the comment of one thread being processed by two or more cores....there is no logical (as in 0's and 1's) way to explicitely do one thing by having two things attempt to work on it if that one thing cannot be converted into two things. I.e. the only way a single-thread could be processed by two or more cores is if the single-thread really had intrinsic multi-thread characteristics but for whatever reason the single-thread was not coded as a multi-thread.

So you can hardware reverse compile the thread and force parts of it (albeit with substantial processing overhead in its own right, recompiling on the fly as it were) to be multi-threaded but this merely accomplishes what could have been done with a rewrite/recompile of the source to take advantage of multi-threads in the first place.

In other words your older software from the pre-multicore days can be pseudo-multicored. This is logically possible. But a thread which is inherently a single-thread because it is truly a sequential instruction thread with zero parallelizations simply can never be parallelized.

You can do smoke/mirror things with latencies and parallel speculative processing relating to the single-thread, but you simple cannot make 1 instruction = 0.5 instruction + 0.5 instruction and claim you have put two cores to work.

There is no "but the guru's could do it, hypothetically, blah blah". It doesn't work that way. Amdahl and company were superbly intelligent folks in the 60's, they did not simply overlook the logic of the math here.

Second, regarding 32nm and 3-D gates, Intel would not implement HK/MG as a one-node solution. If you know anything about process development and technology nodes then I should not have to say anything more. 3-D gates will have already been assessed and deemed not necessary until at least the 22nm node...the proof of which is contained in the fact that 45nm is planar CMOS with HK/MG xtors.

If 45nm = planar CMOS with HK/MG (1st node introduction) then 32nm = planar CMOS with HK/MG (2nd node introduction).

22nm would be the first opportunity that Intel would take to introduce anything significantly new into the xtor...3D gates would qualify as something significantly new.

Very interesting read .

But so is this .

http://www.intel.com/technolog...ive-threading-1205.htm

Their are more info from intel on mitosis and they even show a demo. of it working . I won't get link because its been posted in this forum more than once .

On the tri gate thing .

http://www.intel.com/technolog...-gate-demonstrated.htm

http://download.intel.com/tech...te_paper_VLSI_0606.pdf

This link here already shows that intel is behind on their introduction to tri gates.

http://m.news.com/Intel+puts+T...63-1006_3-1015424.html

One must keep in mind that it was IBM who said that high k and metal gates wasn't feasable till 32nm process . It is in fact Intel that moved first on it at 45nm. Only after this did IBM say ya we have that also . I suspect that IBM's will be better tho as it will likely be a dual gate process.

I look for Intel tri-gates at 32nm. When all others were dening intel would have High K and metal gates at 45nm . I stuck to my guns and insisted that it would appear on 45nm. I will stick with my guns and insist that we will see tri gates on intels 32nm process Nehalem C. This isn't something to argue about its only speculation . But all info from intels says tri-gates on 32nm process.