A few key points ~
At IDF, Intel had a gigantic 3D model on stage. We learned during the original announcement that Intel is building its first 3D XPoint iteration on the 20nm process with a 128Gb die density, and that there will initially be two layers. The technology could be scaled by stacking layers higher, and eventually by shrinking lithography.
We learned that 3D XPoint used a bulk material property change (rather than a stored charge) to address each cell. This provides a level of granularity we havent seen before, and subsequently offers better scalability and higher performance. However, we didnt learn what that material change process would be.
How It Actually Works
Which is to say, what is the bulk property change technology in play?
In a sit-down chat with Crooke during IDF, we asked him three different ways what technology 3D XPoint was using. His first answer was simply that it was new and it is 3D XPoint. He also wondered why everyone was so focused on the property change mechanism (some have said PCM, some ReRAM), saying, "its recreational to some extent how were accomplishing that." His third reply was simply that it was a competitive advantage, meaning we wont know until it is impossible for Intel to keep it from us.
DIMMs And JEDEC Compliance
One new item Crooke revealed on stage at IDF was that 3D XPoint would ship in memory-mapped devices (DIMMs). We asked him whether they'd be JEDEC-compliant and he replied they'd be compatible with DDR4 mechanically and electrically, but that the technology would require a new interface since it is non-volatile, and that Intel was integrating it into its platforms.
When asked if it was an NVDIMM by JEDEC standards, Findley answered, simply, "No." When asked if it will leverage a proprietary protocol that would remain proprietary to Intel, he answered, simply, "Yes." Moreover, when asked again whether it would be JEDEC-compliant, he replied, "Not at this time."
Will performance and cost be closer to DRAM or NAND?
Intel tossed around some high-level figures, but was not specific. There was no discussion about pricing, even on a percentage basis.
Intel has been a staunch proponent of the new NVMe (Non-Volatile Memory Express) protocol, a lightweight register interface constructed from the ground up with future non-volatile memory technologies in mind (not NAND).
In fact, Intel established the NVMe standards committee, which consists of every major memory manufacturer. Intel recently revealed that it founded the NVMe development committee specifically with the goal to provide a refined interface to empower 3D XPoint-based products. Yes: In an odd twist of fate, Intels own competitors helped pour fuel onto the 3D XPoint fire.
The interface is the key; connecting 3D XPoint via the NVMe interface brings a 10x reduction in latency compared to a standard NAND-based NVMe SSD. Utilizing other protocols, such as AHCI or SCSI, would saturate the CPU with computational overhead long before the system reaped the latency and performance rewards of the underlying medium.
SourceDRAM/NAND Market Impact
Surprisingly, during Micron's Summer Analyst Conference, CEO Mark Durcan indicated that 3D XPoint could equate to almost half of Micron's DRAM business in 2018, saying: "In terms of how quickly will this market grow and how quickly well become significant, I think that is hard to know exactly today...the 2018 timeframe could easily be of the same order of magnitude as our DRAM businesses in that timeframe. So maybe not the same size, maybe half the size in 2018, but it will be a significant additive revenue stream to Micron at the time."
Durcan could be referring to the revenue 3D XPoint generates, or he could be referencing the bit output, which leaves his statement open to interpretation. In either case, Durcan is indicating 3D XPoint will be comparable to Microns $40+ billion DRAM business in two short years. This is an incredibly bullish statement, and it is hard to imagine that amount of production will not affect the DRAM or NAND segments.
The DRAM and NAND markets serve as an oasis of stability for Micron, and both it and Intel have gone to great pains to assuage skittish investors by indicating that 3D Xpoint will not cannibalize DRAM or NAND markets, but will be additive. This, too, is quite optimistic, and it would be more realistic to imagine it eating into a little of both.
The more interesting side effects of 3D XPoint will likely come from IMFTs competition. Samsung, in particular, is in a nice spot to flood the market with either of the opposing NAND or DRAM mediums. It is in the process of building a $23 billion fab that will be operational by 2017, and that, by some estimates, is large enough to equal the 300mm wafer production of SK Hynix and SanDisk combined.
Samsung isnt commenting on what its "superfab" will be used for, but it can pump out either NAND or DRAM. If Samsung chooses to flood the market with cheap NAND on one end and cheap DRAM on the opposite end, it can create enough price pressure to relegate 3D XPoint to niche applications, at least until Samsung is ready to roll out its competing technology.
Cue the return of the zero-margin DRAM market endured by the memory manufacturers over the last decade. Admittedly, this would be a bit of a nuclear option for Samsung, as it would also pay dearly in margins, but the key takeaway is that the company has the option of pushing the red button.
SK Hynix also recently announced it is investing $38.9 billion for three semiconductor fabs, so the attacks could come from multiple angles. Another possibility is that IMFTs competitors could embrace, or create, an industry standard protocol for their own non-volatile products, which would fly in the face of Intel's proprietary interconnects.
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