Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025		Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Clockspeed.png
 

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Geddagod

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msj10 said:
View attachment 80468

Interesting pic of Lunar Lake showing the layout of the cores.
Click to expand...
Hah. The twitter user who leaked this a month? or two ago deleted this in the comment thread he originally posted it. IIRC he said he got it from chiphell? Again, doubt it's fake though.
I'm assuming this is a thermal test platform for early, early silicon of LNL (on TSMC 3nm, come at me A/// lol) . Apparently the 'compute' tile on LNL contains a lot more than just the CPU cores- iGPU, LP cores, and SLC.
The picture doesn't tell you a lot (other than confirming the 4+4 config), and I think the E-cores this time around will actually be used like how Apple uses their small cores, turning them on for idle and low power tasks as to not bother the big cores, and being able to isolate the cores much better than what Intel does with big.little on laptops right now.
As in Intel might not need to include a 'low power island' on the soc tile with LNL to preserve battery life.
Just for kicks and giggles if anyone cares, the 4 big cores on this picture *very inaccurate due to it looking like thermal testing with no clear boundaries* is ~28mm^2 IIRC (did the math a while ago and rn I'm stressed about my math test tmmrw lol).
That's also not too far off from what a RWC 4C complex with L3 would be. So despite being a node shrink, being around the same area implies bigger cores or more cache, aka higher ipc/better efficiency.
 
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msj10

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Geddagod said:
Just for kicks and giggles if anyone cares, the 4 big cores on this picture *very inaccurate due to it looking like thermal testing with no clear boundaries* is ~28mm^2 IIRC (did the math a while ago and rn I'm stressed about my math test tmmrw lol).
Click to expand...
the P-core looks smaller to me relative to the E-cores than RWC or GLC was but like you said it's very difficult to draw any conclusions from this.
 
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Geddagod

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msj10 said:
the P-core looks smaller to me relative to the E-cores than RWC or GLC was but like you said it's very difficult to draw any conclusions from this.
Click to expand...
I think finding the P-core itself is pretty much impossible to find the size of from this pic. My 28mm^2 estimation was the entire 4C cluster, as in core, L2, L3, ringbus, the works. Pretty much just that giant top rectangle with all 4 big cores in it, with the 17.4mm line as scale.
The reason I said it looks similar size to RWC was, from a quick discord search from a server I'm on lol, 8RWC+24MB L3 = 63mm^2, half of that would be ~30, around the same as a 4C LNC cluster according to the pic.
A node shrink + new arch usually results in the new core being 60-80% the size of the previous one (sandy bridge vs haswell, haswell vs skylake, skylake vs sunny cove). I don't think LNC is going to be much different, though I will say the trend of the next arch+node core shrinking has been a slowly dying trend it looks like.
 
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Geddagod

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I do want to add something kinda weird about that pic tho, if it is a thermal image...
Why does it look like the decode/load/store were the hottest parts of the core? Isn't GLC's decoder clock gated like 80% of the time? I always assumed that honor went to the FPU.
And where is the adjacent L3 slice for the little cores?
 
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msj10

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Geddagod said:
I think finding the P-core itself is pretty much impossible to find the size of from this pic. My 28mm^2 estimation was the entire 4C cluster, as in core, L2, L3, ringbus, the works. Pretty much just that giant top rectangle with all 4 big cores in it, with the 17.4mm line as scale.
The reason I said it looks similar size to RWC was, from a quick discord search from a server I'm on lol, 8RWC+24MB L3 = 63mm^2, half of that would be ~30, around the same as a 4C LNC cluster according to the pic.
A node shrink + new arch usually results in the new core being 60-80% the size of the previous one (sandy bridge vs haswell, haswell vs skylake, skylake vs sunny cove). I don't think LNC is going to be much different, though I will say the trend of the next arch+node core shrinking has been a slowly dying trend it looks like.
Click to expand...
I am not disagreeing that it can be a similar size to RWC, I am saying that relative to the E-cores it looks smaller, that could be because Skymont got bigger.
 
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Geddagod

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Henry swagger said:
https://twitter.com/x/status/1655593409464205312
Redwood cove looks like golden cove supercharged.. l2 structure
Click to expand...
Waiting for Tom to explain to his viewers how Intel engineers thought the relatively minor changes in RWC vs GLC was going to cause a 20% IPC gain.
Full disclaimer, I'm no chip architect, but to me crestmont looks like it saw more/bigger architectural changes vs gracemont than rwc did vs glc. While there is no specific bottleneck breakdown for GRC, for modern cores isn't the front end almost always the bottleneck? And wasn't the renamer in most archs (and GRC too I'm pretty sure) the limit to max theoretical ipc to the core as well?
The RWC L1 changes look interesting, but I suspect that it would add extra cycle(s) of latency, limiting performance benefit. Perhaps they did it for efficiency and to better feed their wide decoders, idk. I do think it's interesting though, AMD has very large uOP caches while Intel looks to be going wide decode + larger caches in order to feed the rest of the core.
 
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Henry swagger

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Geddagod said:
Waiting for Tom to explain to his viewers how Intel engineers thought the relatively minor changes in RWC vs GLC was going to cause a 20% IPC gain.
Full disclaimer, I'm no chip architect, but to me crestmont looks like it saw more/bigger architectural changes vs gracemont than rwc did vs glc. While there is no specific bottleneck breakdown for GRC, for modern cores isn't the front end almost always the bottleneck? And wasn't the renamer in most archs (and GRC too I'm pretty sure) the limit to max theoretical ipc to the core as well?
The RWC L1 changes look interesting, but I suspect that it would add extra cycle(s) of latency, limiting performance benefit. Perhaps they did it for efficiency and to better feed their wide decoders, idk. I do think it's interesting though, AMD has very large uOP caches while Intel looks to be going wide decode + larger caches in order to feed the rest of the core.
Click to expand...
Redwood cove will have even more l1 bandwidth.. the old leaks mention that.. yeah i think crestmont will have big ipc if they increase the robs to 320+ .. they.l reach rocket lake zen 3 ipc 😃
 
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Exist50

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Geddagod said:
Isn't GLC's decoder clock gated like 80% of the time? I always assumed that honor went to the FPU.
Click to expand...
I think the OOO is typically a hotspot. Maybe the FPU if you're running a power virus, but we don't know the workload in question here. Also, if we're ever to see a fundamental relayout of the core, it would be with Lion Cove, so mapping to particular structures is likely impossible without more information.
 
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A///

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that would depend on intel and microsoft working on the scheduler so it behaves as apple does it or else it'll be a sliding scale of how accurately it assigns tasks.

Geddagod said:
I'm assuming this is a thermal test platform for early, early silicon of LNL (on TSMC 3nm, come at me A/// lol) . Apparently the 'compute' tile on LNL contains a lot more than just the CPU cores- iGPU, LP cores, and SLC
Click to expand...
Got my club ready but would rather a cinder block. you'll get your atta boy when a product comes out on that node.
 
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SiliconFly

SiliconFly

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mikk said:
What CPU is this:

https://twitter.com/x/status/1659910610208063490

2MB L2 means it's Raptor or something newer. iGPU is a 128EU variant at 2100 Mhz, it can't be Raptor. Meteor Lake or Arrow Lake? 22CU could be 6+16 because of 22 cores. 24MB L3 means it's probably a version with 6 big cores. So maybe 6+16 or it's a wrong detection with 6+8.
Click to expand...
Looks more like MTL ES. But why is it reporting the cores as 16C/32T?
 
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jpiniero

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mikk said:
2MB L2 means it's Raptor or something newer. iGPU is a 128EU variant at 2100 Mhz, it can't be Raptor. Meteor Lake or Arrow Lake? 22CU could be 6+16 because of 22 cores. 24MB L3 means it's probably a version with 6 big cores. So maybe 6+16 or it's a wrong detection with 6+8.
Click to expand...

Meteor possibly, 6+8+2. Threads is just a misdetection. GPU could be an Arc ES/rebrand it doesn't detect correctly either.
 
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Exist50

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trivik12 said:
its meteor going by oneraichu and wild_c at twitter. Also oneraichu is saying Intel 4 is "2nd gen" 7nm.

https://twitter.com/x/status/1659978808026632194
Click to expand...
You can find a lot of references in old leaks that hint towards "Intel 4" being second gen. p1276.31 and 7nm HLL+ have both been mentioned as old or internal names. Afaik, first gen 7nm was what they intended to use for Ponte Vecchio, before that was switched to TSMC.
 
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DrMrLordX

DrMrLordX

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If true, that is unfortunate. Not that many Raptor Lake Refresh owners would have wanted to "upgrade" to a limited selection of 6P+8e CPUs, but there could have been a niche for a performance-oriented model with that core layout. Somewhere. At least the benchmark comparisons would have been enlightening.
 
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DrMrLordX

DrMrLordX

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igor_kavinski said:
I bet the entire MTL production batch has been pre-booked by the OEMs for their laptop designs at least a year or more in advance. Who wouldn't want to sell laptops with Ultra processors? :)
Click to expand...
eh, maybe. Meteor Lake is the only product landing on Intel 4 in any significant volume (that I know of) so it's not like they couldn't just make more. Unless production numbers aren't up to snuff. Not that I want to go back down the "Intel doesn't have enough EUV equipment" trail. By now even Intel should have been able to remedy that problem. Hopefully.
 
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msj10

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I wonder if ARL-S 6+8 will have a new chip or it will just reuse the ARL-P compute die on 20A. it's a shame raichu decided to censor all of that slide, it would've cleared a lot of the confusion.
 
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