Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Exist50]

But that doesn't make sense in several ways. Why waste the area necessary for AVX-512 support if software/OS solution was never in the cards, and continue wasting it after it's even disabled and fused off as an optional feature?

More effort to remove than it's worth, perhaps? And they need it for the server chips anyway.

 

[jpiniero]

As mentioned the decision to fuse off was at the last second.

 

[BorisTheBlade82]

As mentioned the decision to fuse off was at the last second.

After the last second, to be precise 😉
As we all know the first batch was delivered without fusing it off

 

[coercitiv]

But that doesn't make sense in several ways. Why waste the area necessary for AVX-512 support if software/OS solution was never in the cards, and continue wasting it after it's even disabled and fused off as an optional feature?

Remember, Alder Lake was not the first Intel product to take this odd path. Lakefield also had no AVX-512 support and yet the transistors were there. It went as far as Intel claiming they had removed the AVX-512 unit, only for Anandtech to report it was still there in the die shots.

 

[moinmoin]

More effort to remove than it's worth, perhaps? And they need it for the server chips anyway.

So you expect MTL to include AVX-1024 for the server chips (where it gets doubled again) only to be fused off again to work along AVX2 capped E cores?

But the E cores were introduced because Core cores got oh so huge and Intel needs area efficient cores to be able to be competitive in the market?

I guess I should just stop trying to make sense of this whole top to bottom mess.

Lakefield also had no AVX-512 support and yet the transistors were there.

Lakefield got the questionable distinction of being one of Intel's most quickly discontinued products. The other chips we talk about are supposedly mainstream chips.

 

[Exist50]

So you expect MTL to include AVX-1024 for the server chips (where it gets doubled again) only to be fused off again to work along AVX2 capped E cores?

I'm expecting that "AVX-1024" doesn't exist at all, but that rumor is for Lion Cove anyways. Redwood Cove probably has the same arrangement we see today.

 

[Shmee]

Hello, I just wanted to remind everyone, that profanity/swearing is not allowed in the technical forums. I know most of you have been good about this, but there have been too many instances of slips in this thread. Thank you for your cooperation.

AT moderator Shmee

 

[Markfw]

Hello, I just wanted to remind everyone, that profanity/swearing is not allowed in the technical forums. I know most of you have been good about this, but there have been too many instances of slips in this thread. Thank you for your cooperation.

AT moderator Shmee

Just a note: Most of the infractions have been variants of the "S" word. Its a 4 letter word, and is prohibited on TV, so its not just US that are restricting it.

 

[Hulk]

Here's my take on why AVX512 is in Golden/Raptor cove but not available to be used with the E cores, which do not have the required structures.

Alder Lake was a big project for Intel. New variant of the big core, new variant of the small core, both on one chip, making them work together (Thread Director), lots of big decisions and quite a bit of R&D to get it all working in a timely manner after the 10nm fiasco. I could see the LAST thing they would want to worry about was designing a P core with (server parts) and without AVX512. In addition, since the previous incarnation of this part has AVX512 the path of least resistance and issues down the road would be to leave it in, get the darn thing working and fabbed. We'll figure out if we need AVX512 capability or will use that area for other structures later. For not we'll eat the die area.

Another big fail/delay for Intel could have been the beginning of a tipping for point for the company. Imagine Intel still farting around with 8 core Rocket Lake variants on the desktop now while AMD has the Zen 4 line up. They would have been irrelevant. That would have been far more disastrous than wasting a little area on AVX512 for the security of knowing, "It works as is, leave it alone. Plus we might need it later."

 

[Tigerick]

Embracing Chaos: The Imperfect Art of Semiconductor Manufacturing And Lithography

5 Longs, Intel EUV Delayed Again, And More

www.semianalysis.com

"EUV is a process fraught with complexity, uncertainty, and imperfection, yet it works. TSMC, Samsung, and SK Hynix are all in production of EUV at varying volumes. Intel has also confidentially stated that they are manufacturing ready for EUV lithography in their Intel 4 process node. We don’t really believe them because internal documents we obtained show Intel’s first high-volume product utilizing EUV, Meteor Lake, has been delayed yet again, with “ready-to-ship” dates delayed until Week 52, 2023 at minimum. This suggests that Intel is facing challenges in implementing a production-scale design into an EUV process technology."

Delay until Week 52 at minimum, why I am not surprise at all?

 

[Doug S]

"Week 52" sounds suspiciously like it might be a repeat of 2018's Cannon Lake special to meet an investor commitment, rather than actual mass production shipments.

 

[igor_kavinski]

We don’t really believe them because internal documents we obtained show Intel’s first high-volume product utilizing EUV, Meteor Lake, has been delayed yet again, with “ready-to-ship” dates delayed until Week 52, 2023 at minimum.

I think Intel will scamper to do a limited release of Meteor Lake soon, with whatever usable dies they can salvage from the mountains of desecrated silicon scrap.

RIP, EUV-fied dead silicon dies.

Someone better start looking at Google maps to identify big trash trucks taking away the dead silicon.

 

[Kocicak]

Seeing how complicated and problematic EUV is, I have no idea what comes after it and how long it takes, we might be well right at the limits of the current technology and A LOT will need to change before we can go further.

Anyway, looking forward to refreshed monolithic Raptor lake, with super massive 1 thread P cores and enhanced E cores, which perform 90% as well as the current P cores do. Go Intel!

 

[Exist50]

Embracing Chaos: The Imperfect Art of Semiconductor Manufacturing And Lithography

5 Longs, Intel EUV Delayed Again, And More

www.semianalysis.com

"EUV is a process fraught with complexity, uncertainty, and imperfection, yet it works. TSMC, Samsung, and SK Hynix are all in production of EUV at varying volumes. Intel has also confidentially stated that they are manufacturing ready for EUV lithography in their Intel 4 process node. We don’t really believe them because internal documents we obtained show Intel’s first high-volume product utilizing EUV, Meteor Lake, has been delayed yet again, with “ready-to-ship” dates delayed until Week 52, 2023 at minimum. This suggests that Intel is facing challenges in implementing a production-scale design into an EUV process technology."

Delay until Week 52 at minimum, why I am not surprise at all?

Given Dylan's history of Meteor Lake claims, I'd hesitate to take that at face value. And even if you believe the underlying "evidence", Meteor Lake's design health is more likely to be a problem than Intel 4 yield.

 

[igor_kavinski]

Seeing how complicated and problematic EUV is, I have no idea what comes after it and how long it takes, we might be well right at the limits of the current technology and A LOT will need to change before we can go further.

The horizon just keeps expanding because human ingenuity is virtually limitless.

Anyway, looking forward to refreshed Raptor lake, with super massive 1 thread P cores and enhanced E cores, which perform 90% as well as the current P cores do. Go Intel!

That would be a new arch, not a refresh, if the E-cores get a boost like that.

 

[Markfw]

Seeing how complicated and problematic EUV is, I have no idea what comes after it and how long it takes, we might be well right at the limits of the current technology and A LOT will need to change before we can go further.

Anyway, looking forward to refreshed monolithic Raptor lake, with super massive 1 thread P cores and enhanced E cores, which perform 90% as well as the current P cores do. Go Intel!

Why is it then that TSMC has no problem with EUV ? They have more experience, thats what. Intel is just learning, there is nothing at the limits of current technology in EUV processing.

As for your second comment, see Igors post above this.

 

[Kocicak]

That would be a new arch, not a refresh, if the E-cores get a boost like that.

What about DEEP refresh?

Does a new architecture mean just adding and cutting stuff without changing any principles of how things function, or is function improvements (as branch predictions etc.) necessary for a new architecture?

I believe that resizing, ommiting and adding stuff without changing any function principles may not be that complicated...

 

[Hulk]

Why is it then that TSMC has no problem with EUV ? They have more experience, thats what. Intel is just learning, there is nothing at the limits of current technology in EUV processing.

As for your second comment, see Igors post above this.

I remember a story my Internal Combustion Engines professors told us when I was studying ME at Rutgers in the '80's. Someone asked him why the Japanese and especially Honda were able to produce us great 4 cylinder engines. They were durable, very balanced at high speeds, light, good HP and economy, easily met emission standards. GM's effort with the 2.3L Quad 4 was crude in comparison.

He said when he got to visit the Honda R&D center in Japan he noticed about 100 intake manifolds, all with small differences that Honda had made for testing. Rigorous meticulous methodology that requires above all else patience and the discipline to keep at it over and over again until you figure it out.

 

[Thunder 57]

Seeing how complicated and problematic EUV is, I have no idea what comes after it and how long it takes, we might be well right at the limits of the current technology and A LOT will need to change before we can go further.

Anyway, looking forward to refreshed monolithic Raptor lake, with super massive 1 thread P cores and enhanced E cores, which perform 90% as well as the current P cores do. Go Intel!

Still bitter that AMD didn't release a "3600 x2" that cost less than a 3800X years ago?

 

[controlflow]

Seemed interesting until I realized it is from Dylan and "Semianalysis". Best to wait for credible sources.

 

[Markfw]

What about DEEP refresh?

Does a new architecture mean just adding and cutting stuff without changing any principles of how things function, or is function improvements (as branch predictions etc.) necessary for a new architecture?

I believe that resizing, ommiting and adding stuff without changing any function principles may not be that complicated...

You are not a CPU designer. If you were, you would not make ridiculous claims. ANYTHING you do to a CPU design has all sorts of implications, look at 3d v-cache. A simple addition ? NO, had to change power parameters and core speed and CO curve.

 

[Tigerick]

Below is my understanding of upcoming Meteor Lake and Arrow Lake CPU and I am trying to calculate how much power needed in TDP term.

	13th RPL-H	MTL-H	ARL-HX
Release Date	Q1 2023	Q1 2024?	Q1 2025?
Process Node	Intel 7	Intel 4 + N5 + N6	Intel 20A + N5 + N6
CPU Max Cores	6P + 8E	6P + 8E	8E + 16E
L3 Caches	24MB	24MB	36MB
P Core Base Clock	2.6 GHz	?	?
P Core Turbo Clock	5.4 GHz	?	?
iGPU	96 EU - 1.5GHz	GT2 Xe LPG 64EU - ?	GT2 Xe LPG 64EU - ?
TDP	45 W	45 W	55 W
Max Turbo Power	115 W	?	?
CPU Tile	NA	25 W	35 W
SoC + IOE Tiles (est)	NA	10 W	10 W
GPU Tile (est)	NA	10 W	10 W
Power per CPU core (4E ~ 1P)		3.13 W	2.92 W

• As far as I understand, SoC tile is the one receiving power from the socket then distribute to other tiles (namely CPU, GPU and IOE) through die to die connectors. That's why I figure SoC tile consume much more power than conventional PCH. For simplification, I combine SoC and IOE tiles as total power of 10W.
• GPU tiles are based on Alchemist graphics engine; so I calculate upon A370M's TGP of 35W. With half of Xe cores and newer process, 10W seems reasonable?
• That left 25W for CPU tile; here comes the interesting part cause this is Intel's first CPU that based on EUV lithography and I am expecting higher clock speed. For reference, AMD's Phoenix has TDP of 35W with base clock speed of 4 GHz and 2.8GHz iGPU speed which are rather impressive. Power per core figures might be good indicator of process advancement in the future cause AMD and Intel are moving to chiplet/tile design...

 

[Exist50]

As far as I understand, SoC tile is the one receiving power from the socket then distribute to other tiles (namely CPU, GPU and IOE) through die to die connectors.

Extremely unlikely. All the chiplets probably receive their power through the package / TSVs through the base die. So in that sense, it's likely similar to current designs.

 

[A///]

I've worked on cpu designs, ARM designs and other things granted not x86 but they still count. Lot's of crap is said. I ignore it and move on.

Looks like Intel is releasing products on 2 and 1.8 nm releasing next year and their IFS client list is moving forward. Has Gelsinger managed to pull off a small but measurable win? WOn't know until next year. But for now I suspect Gelsinger's jewels are off the chopping block.If Intel can level to TSMC in a year or two, big IF there, then it's going to revive the race with them and it'll push AMD to design a highly competitive product to blow past by Intel thus benefiting the customers.I wouldn't mind paying 800-900 usd for a 24 core 48 thread processor with avx512 and other AI neural stuff built in, that clocks high and better RAM speeds that can be OC'd to higher numbers and has decent power savings over whatever Intel has in plan. If Intel can figure out HT and avx512 on their e-cores then it's going to be an interesting fight between them and AMD. For now AMD will keep chipping away at Intel's shares like a nagging wife to her husband's patience.

 

[Tigerick]

Extremely unlikely. All the chiplets probably receive their power through the package / TSVs through the base die. So in that sense, it's likely similar to current designs.

Above slides seem indicating Die2Die power delivery from SoC, is it?