Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+4+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Doug S]

Well, what is the M1 Pro to you?

It is a monolithic SoC closely bonded to DRAM chips. That's not breaking up functionality that was formerly shipped in the same piece of silicon. The only "chiplet" design Apple has is the M1 Ultra, and they have no choice there. Two M1 Max would be a bit too large to fit within an EUV reticle, and they knew they were going to do 2x bigger yet for the Mac Pro.

A lot of what we are seeing is necessity. With high NA EUV the reticle size will be cut in half to 429 mm^2, and is much less square so the practical limit for maximum floorplanning flexibility is probably more like 350 mm^2. There are some yield benefits to making 4 100 mm^2 chips instead of 1 400 mm^2 chip, especially at lower volumes, but I don't see the cost/benefit working at say 150 mm^2. What the crossover is, I have no idea - we'll probably see different decisions on that from different companies. But high NA EUV means companies want to be ready now since it is only a few years away.

There's a reason Apple is not and will not go chiplets with their mobile SoCs, when they are all the same and small enough that yield isn't much of an issue. Now one exception may be when they start making their own modems, they probably make them separately for a couple years before they become integrated onto the SoC like Qualcomm does with theirs.

 

[DrMrLordX]

I was also quite surprised they would not use EMIB. But 22nm seems to make this very cheap and maybe their older factories would otherwise face low demand.

Keep in mind that if you're referring to 22FFL, it isn't actually in the Intel 22nm family. It's a 14nm variant.

 

[BorisTheBlade82]

Keep in mind that if you're referring to 22FFL, it isn't actually in the Intel 22nm family. It's a 14nm variant.

Yes, exactly. And they might have huge amounts of free capacity after their 14nm lineup disappears from more and more markets. TBH I don't know if and when they will open these fabs to the foundry business where a lot of demand from automotive etc. could be had.

 

[DrMrLordX]

Yes, exactly. And they might have huge amounts of free capacity after their 14nm lineup disappears from more and more markets. TBH I don't know if and when they will open these fabs to the foundry business where a lot of demand from automotive etc. could be had.

Intel is getting wrecked trying to peddle Cascade Lake so yeah, they should have a fair amount of 14nm++ capacity available. I'm not exactly sure how easy it will be for them to pivot to wide-scale 22FFL production, but they can probably do it. Whether or not shareholders will like this strategy is another matter.

It's safe to say that they will have plenty of relatively low-cost 22FFL available for their own IDM products.

 

[msj10]

https://twitter.com/x/status/1572041271853879296

Please remember to include personal commentary in the CPU forum. A link or picture is not sufficient. Here is a link to the CPU forum rules https://forums.anandtech.com/thread...f-current-rules-rules-updated-5-4-20.2332179/
Thanks -AT Moderator Shmee

 

[igor_kavinski]

I assume it's teething problems due to early hybrid implementation combined with competitive pressure(performance).

Constantly moving threads between P-cores and E-cores courtesy of Intel Thread Director could be what's burning unnecessary power.

 

[igor_kavinski]

Found this on Phoronix: https://lpc.events/event/16/contributions/1191/attachments/1074/2125/LPC-2022-1-freq.pdf

Intel engineers pointing out issues caused in Linux by the hybrid approach. I suppose they can't do the same for Windows without incurring Microsoft's wrath.

 

[poke01]

Intel engineers pointing out issues caused in Linux by the hybrid approach. I suppose they can't do the same for Windows without incurring Microsoft's wrath.

The only Operating systems who got hybrid SoC's/CPU scheduling 99.99% right is Android and iOS/macOS.

Windows and Linux have issues right now but it could also be Intel's coding.

 

[igor_kavinski]

it could also be Intel's coding.

Intel has a lot to learn in the hybrid computing realm. They could have gained a lot of relevant experience if they had stuck to their guns and made Atom a viable smartphone CPU.

 

[moinmoin]

The only Operating systems who got hybrid SoC's/CPU scheduling 99.99% right is Android and iOS/macOS.

Windows and Linux have issues right now but it could also be Intel's coding.

Android systems to this day are using Linux kernels. Intel's approach to hybrid appears to be too different to profit from existing optimizations for ARM chips (which may well be partly in hardware).

 

[igor_kavinski]

I will be surprised if Intel doesn’t have a new enthusiast level chip in 2023. Are you saying this will be the case? IIRC Arrow Lake is a 2024 product.

They will release the KS SKU in June/July 2023...

I can't see them doing anything else.

 

[igor_kavinski]

Yeah, but that's gonna make the shareholders really mad. Margins margins margins.

Tell the shareholders, if we don't offer discounts, revenue may drop.

Shareholders: DISCOUNT THEM!!!

 

[eek2121]

The only Operating systems who got hybrid SoC's/CPU scheduling 99.99% right is Android and iOS/macOS.

Windows and Linux have issues right now but it could also be Intel's coding.

As another user mentioned, Android uses Linux as a base, though there are large differences.

That being said, Windows and Linux both don’t know how to deal with hybrid CPUs out of the box. Developers on both sides of the fence need to learn from Apple.

 

[DrMrLordX]

Developers on both sides of the fence need to learn from Apple.

Or pretty much any other ARM vendor? Qualcomm and Mediatek (for example) have three different core types in their flagship mobile SoCs right now.

 

[igor_kavinski]

NM

 

[IntelUser2000]

Constantly moving threads between P-cores and E-cores courtesy of Intel Thread Director could be what's burning unnecessary power.

It's not. As demonstrated by the one system having rather fantastic battery life.

Alderlake came out earlier than most expected. Sometimes that's why people prefer a Tick such as Raptorlake because it covers up the warts introduced by the new features in the Tock chip. That's not only in performance, but market positioning as well.

 

[igor_kavinski]

As demonstrated by the one system having rather fantastic battery life.

Sorry to bother you but which one?

 

[IntelUser2000]

@igor_kavinski No problem, but I did post it before.

Post #17352, in the major Intel -Lake thread. Page 695.

https://www.notebookcheck.net/Dell-XPS-13-9315-laptop-in-review-Low-performance-incredible-battery-life.640173.0.html

The review criticizes it for having low performance but the performance it shows is over 2x what previous generation -Y parts were and is comparable to 25W Icelake, and 15-18W Tigerlake. And I am talking about sustained performance since I don't really care about peak for MT workloads.

2x perf/watt.

Remember, between the original Core M in 2015 and Amberlake Y in 2019, there was maybe 20-30% performance boost. That's pretty much a standstill. Also, with Y parts you had to sacrifice serious amount of single threaded performance. Alderlake on that system does substantially well compared to Alderlake-U.

 

[poke01]

@igor_kavinski No problem, but I did post it before.

Post #17352, in the major Intel -Lake thread. Page 695.

https://www.notebookcheck.net/Dell-XPS-13-9315-laptop-in-review-Low-performance-incredible-battery-life.640173.0.html

The review criticizes it for having low performance but the performance it shows is over 2x what previous generation -Y parts were and is comparable to 25W Icelake, and 15-18W Tigerlake. And I am talking about sustained performance since I don't really care about peak for MT workloads.

2x perf/watt.

Remember, between the original Core M in 2015 and Amberlake Y in 2019, there was maybe 20-30% performance boost. That's pretty much a standstill. Also, with Y parts you had to sacrifice serious amount of single threaded performance. Alderlake on that system does substantially well compared to Alderlake-U.

One reason for great battery life is the 1200P(FHD+) display. That Dell laptop is not configured with a 1440P nor a 4K panel. Take a look at this video. Alderlake does not great battery life when compared to current market CPUs/SoCs.

The laptop tested is the Dell XPS Plus with the i7 1260P with a 55Whr battery and it got 4hrs of battery life. The M2 MacBook Air however got 12 hrs with a smaller battery(52Whr). Intel needs to work out its "boosting" issues for simple things like opening websites because thats the default setting.

 

[IntelUser2000]

One reason for great battery life is the 1200P(FHD+) display. That Dell laptop is not configured with a 1440P nor a 4K panel. Take a look at this video. Alderlake does not great battery life when compared to current market CPUs/SoCs.

Nah, that's not it.

https://www.notebookcheck.net/Dell-XPS-13-Plus-laptop-review-Is-the-base-configuration-the-best-choice.640441.0.html

The 1240P version with the FHD(not even FHD+) is mediocre in battery life. The FHD 1240P version is only about 15% better? Alderlake as a whole in general gets 20% less, meaning Tigerlake does 25% better! You can see from multiple reviews that most Alderlake systems can't reach very low package power figure even in idle - the above mentioned system does.

The above mentioned system is mere 10% away from the Apple Mx chips. Yea, it's slower but the battery life is there, indicating it's not something stupid like ISA, but poor execution over years on Intel side, and lack of real focus to get power down for whatever reason.

Another great thing the review I mentioned demonstrates is that it's not a regression in battery life over predecessors. Other Alderlake chips are!

 

[poke01]

Nah, that's not it.

https://www.notebookcheck.net/Dell-XPS-13-Plus-laptop-review-Is-the-base-configuration-the-best-choice.640441.0.html

The 1240P version with the FHD(not even FHD+) is mediocre in battery life. The FHD 1240P version is only about 15% better? Alderlake as a whole in general gets 20% less, meaning Tigerlake does 25% better! You can see from multiple reviews that most Alderlake systems can't reach very low package power figure even in idle - the above mentioned system does.

The above mentioned system is mere 10% away from the Apple Mx chips. Yea, it's slower but the battery life is there, indicating it's not something stupid like ISA, but poor execution over years on Intel side, and lack of real focus to get power down for whatever reason.

Another great thing the review I mentioned demonstrates is that it's not a regression in battery life over predecessors. Other Alderlake chips are!

Yes the Dell XPS with the i5 1230U is the most power efficient Alderlake chip so far that's been tested. Buts that be expected with 8e and 2p cores and the maximum power of 15 watts for PL1. Also the MacBook Air M1 has a 1600p display vs a 1200p display and a smaller battery.

Still great battery from the 15 1230U tho.

ISA never matters. It's always the design and node. Intel really missed the smartphone industry. ARM succeed because Intel failed. Intel won't be a mobile leader till Lunar Lake. It's easy to create a power hungry chip but it takes skill to create a chip that can still be powerful and yet consume less power than the competition.

 

[maddie]

It is a monolithic SoC closely bonded to DRAM chips. That's not breaking up functionality that was formerly shipped in the same piece of silicon. The only "chiplet" design Apple has is the M1 Ultra, and they have no choice there. Two M1 Max would be a bit too large to fit within an EUV reticle, and they knew they were going to do 2x bigger yet for the Mac Pro.

A lot of what we are seeing is necessity. With high NA EUV the reticle size will be cut in half to 429 mm^2, and is much less square so the practical limit for maximum floorplanning flexibility is probably more like 350 mm^2. There are some yield benefits to making 4 100 mm^2 chips instead of 1 400 mm^2 chip, especially at lower volumes, but I don't see the cost/benefit working at say 150 mm^2. What the crossover is, I have no idea - we'll probably see different decisions on that from different companies. But high NA EUV means companies want to be ready now since it is only a few years away.

There's a reason Apple is not and will not go chiplets with their mobile SoCs, when they are all the same and small enough that yield isn't much of an issue. Now one exception may be when they start making their own modems, they probably make them separately for a couple years before they become integrated onto the SoC like Qualcomm does with theirs.

This ignores one of the huge benefits of chiplets. Node and library optimizations for individual IP blocks leading to area, power & performance gains.

 

[IntelUser2000]

Yes the Dell XPS with the i5 1230U is the most power efficient Alderlake chip so far that's been tested. Buts that be expected with 8e and 2p cores and the maximum power of 15 watts for PL1. Also the MacBook Air M1 has a 1600p display vs a 1200p display and a smaller battery.

My point was that 1230U isn't a regression over previous generation Y parts while the U parts are.

Another review of the same system shows good battery life under video playback but mediocre on web browsing. Clearly there's some optimization issue with Alderlake too - pointing to again immaturity of the platform that may take a Tick like Raptorlake to fix.

Compared to the M1 it's in the ballpark which cannot be said for Intel's other chips.

 

[igor_kavinski]

Buts that be expected with 8e and 2p cores and the maximum power of 15 watts for PL1.

That's probably the secret to the better battery life. Less power hungry threads.

Another review of the same system shows good battery life under video playback but mediocre on web browsing.

P-cores go nuts with power consumption while executing Javascript. It would be interesting to do a web browsing test with noscript.

 

[IntelUser2000]

P-cores go nuts with power consumption while executing Javascript. It would be interesting to do a web browsing test with noscript.

I can't say that yet. I still think it's due to immaturity of the platform. Raptorlake should show maturity in few areas, and this might be one of them. It will address gaps that exist in Alderlake and add some key features. Every Tick chip did that(Penryn/Westmere/Ivy Bridge/Broadwell/Kabylake).

There are over a dozen different knobs related to power management, so the final product has to be very well fine tuned. It might be to get it out little bit earlier they sacrificed the final optimization part. Also with Tigerlake they were seriously behind multi-threaded performance. Eagerness to win in performance(or at least close the gap) could have been a factor as well.