Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7 360	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	4.8 GHz	5 GHz		4.8 GHz
L3 Cache		12 MB	6 MB	12 MB		12 MB
TDP		15 - 55 W	15 - 35 W	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5x-7467	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB	48 GB	32 GB		128 GB
Bandwidth		83 GB/s	60 GB/s	136 GB/s		120 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	2.6 GHz	2 GHz		2.5 GHz
NPU		GNA 3.0	17 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Goop_reformed]

That same argument works in reverse too. It's super weird how Company A and Company B can land at the same performance and yet it's a disaster for one and a success for the other.

No it doesn't, Arrowlake has better nodes, brand new cores. Zen 5 only has 1 of those 3 and the uplift even though is disappointing to me, still larger than that of arrowlake.

 

[H433x0n]

No it doesn't, Arrowlake has better nodes, brand new cores. Zen 5 only has 1 of those 3 and the uplift even though is disappointing to me, still larger than that of arrowlake.

You listed 2 things, not 3.

N3B is advertised as -1% to +4% performance improvement OR +3% to +8% efficiency advantage over N4P. For the few Apple processors that have been fabbed on N3B, the advantage over their N4P products is non existent. Does that sound like a major node advantage to you?

 

[Hitman928]

You listed 2 things, not 3.

N3B is advertised as -1% to +4% performance improvement OR +3% to +8% efficiency advantage over N4P. For the few Apple processors that have been fabbed on N3B, the advantage over their N4P products is non existent. Does that sound like a major node advantage to you?

It has a very big logic density advantage, but the quest for high frequencies and inclusion of large caches probably takes a large part of that off the table as well.

 

[DavidC1]

No it doesn't, Arrowlake has better nodes, brand new cores. Zen 5 only has 1 of those 3 and the uplift even though is disappointing to me, still larger than that of arrowlake.

Seeing the predecessor has two core types, counting two core types as two out of the three makes no sense.

CPUs are a black box from the perspective of the consumer. As long as it's competitive it doesn't really matter. I agree with @H433x0n's POV. If they are same, what's the complaint?

I thought it was amazing when 22nm transistor chips came from Intel, but when I got it in my hands, I realized that part mattered zero to me.

It's interesting how two companies took a very different approach to get to the same point. AMD uses clustered decode to enhance SMT gains, and Arrowlake has great E core gains.

 

[DavidC1]

Let's look at prime examples of why we need to wait:

Back then:

Looking at this, it appears ARL might match or beat the competition in ST.

Now:

If no decent uplift, the P core team needs to be fired.

Every leak and every PPT slide sways the emotions of the people in the forum from one pendulum swing to the other.

Just.... wait.

 

[Goop_reformed]

2 things, not 3.
-1% to +4% performance improvement OR +3% to +8% efficiency advantage over N4P.

Cores not core, so 3.

Regarding the node, let me put it this way. Arrowlake has the best hmv nodes atm, and the jump from Raptor to Arrow is Intel 7 to N3B. That is a full fat node jump, perhaps more.

.

Zen 5C and Zen 5 are essentially the same. The monts and coves are definitely not.
>As long as it's competitive it doesn't really matter.

Oh but it does, the road leading up to that matters a whole lot.

>It's interesting how two companies took a very different approach to get to the same point. AMD uses clustered decode to enhance SMT gains, and Arrowlake has great E core gains.

One approach is vastly superior to the other in terms of cost/development cycles/performance/scaling.

 

[Goop_reformed]

Let's look at prime examples of why we need to wait:

Why the wait? Arrowlake performance is already known at this time.

 

[alcoholbob]

If these leaks come out as true, lion cove seems disapointing, arrow lake seems meh even with the chadmont onboard. Tsmc 3nb, no avx512 and bigger core than z5 for overall similar perf and eficiency? Doesnt seems great for me

AMD has had better efficiency and workstation IPC than Intel for years now, even on inferior nodes. The only reason it was even "close" was the lower latency of the non-chiplet design gave the illusion they were somehow close because Intel had acceptable gaming performance. So this shouldn't be a surprise. Intel is years and years away from catching up to AMD from an architectural standpoint. Having a node advantage isn't going to close the gap.

Intel is like where AMD was vis-a-vis with Nvidia in the GPU market in 2017. Power inefficient, silicon inefficient, and having to clock things to the moon just to get close, and still lose.

 

[AMDK11]

AMD has had better efficiency and workstation IPC than Intel for years now, even on inferior nodes. The only reason it was even "close" was the lower latency of the non-chiplet design gave the illusion they were somehow close because Intel had acceptable gaming performance. So this shouldn't be a surprise. Intel is years and years away from catching up to AMD from an architectural standpoint. Having a node advantage isn't going to close the gap.

Intel is like where AMD was vis-a-vis with Nvidia in the GPU market in 2017. Power inefficient, silicon inefficient, and having to clock things to the moon just to get close, and still lose.

However, I will wait for the final tests and the IPC (LionCove) increase compared to RaptorCove before I finally evaluate ArrowLake.

 

[CouncilorIrissa]

LNC isn't RPC. It was supposed to bring in more IPC.

Intel literally published the data a month and a half ago, +14% over RWC that is marginally slower than RPC. +14% IPC at -8% clock speed compared to 14900KS. Where is the ST uplift supposed to come from?

 

[naukkis]

Intel literally published the data a month and a half ago, +14% over RWC that is marginally slower than RPC. +14% IPC at -8% clock speed compared to 14900KS. Where is the ST uplift supposed to come from?

From decreasing 14900KS clocks. Those st boost clocks come from voltages that silicon couldn't handle so comparison to those are ridiculous. Real sustainable ST uplift from 14900K to Arrowlake might actually be quite large.

 

[coercitiv]

Where is the ST uplift supposed to come from?

It was supposedly going to get more performance by:

• having more cache
• running fabrics at higher speeds, lowering internal latencies overall
• being a different core than mobile LNC, essentially a new "tick" sharing the same LNC name for undisclosed reasons

The last point was deemed the most important while lacking any backing from leaks or Intel tech details. It was essentially made up to suit the narrative, the "possible" was presented as "probable" and repeated until it's fictitious nature became obscured. The same recipe as the AMD hype train from the other thread, with the same shocking revelation when reality checked in.

Don't worry though, by tonight I expect we'll transition into acceptance mode. Soon there will be talks about 200 Mhz higher clocks in final retail units or KS SKU, leaks about higher memory speed support etc. We'll get over it 😀

 

[FlanK3r]

I very much agree, and i have been telling the guys in this thread that have been hyping ~ +20% ST vs 14900K that they would be wise to lower their expectations

IPC is around 10-12%, it is not bad. But of course, 14900K has higher clocks. IPC is measured to same frequency, which propably 14900K will have 5% better.
From my point of view is multicore performance awesome, due fact, there is no HT and 8P+16E cores (so 24C/24T). Seems, small cores will be very strong!

 

[ErichZannMusician]

Lion Cove being +14% IPC vs Redwood Cove IPC is an estimate based on projections made by Intel. It is not the same as AMD's official figures for Zen 5 vs Zen 4 of +16% which is based on internal testing on actual hardware.

In other words, the figure given by Intel is not comparable to the figure given by AMD.

 

[FlanK3r]

Bad is, Redwood is worse than Raptor Cove in average 🙂 But Skymont is another level I think.

 

[mikk]

Lion Cove being +14% IPC vs Redwood Cove IPC is an estimate based on projections made by Intel. It is not the same as AMD's official figures for Zen 5 vs Zen 4 of +16% which is based on internal testing on actual hardware.

In other words, the figure given by Intel is not comparable to the figure given by AMD.

View attachment 103801

Estimate is also tested, Intel always uses the term estimate and people don't get it.

 

[Goop_reformed]

Estimate is also tested, Intel always uses the term estimate and people don't get it.

If that is the case then Lion Cove is only 10% ahead of Raptor Cove IPC wise. That plus the clock regression = single digit single thread uplift.

 

[LightningZ71]

Cores not core, so 3.

Regarding the node, let me put it this way. Arrowlake has the best hmv nodes atm, and the jump from Raptor to Arrow is Intel 7 to N3B. That is a full fat node jump, perhaps more.

It may be a full node jump from a manufacturing point, but, from a chip performance standpoint, not so much. Intel 7 is a several times relaxed version of the 10nm class superfin process. It gave up density multiple times to be able to acceptably yield processors that had a chance of reaching ~6.2Ghz. TSMC N3B is a first pass at a new node with yield difficulties (look at Apple's NGD contract with TSMC for hard evidence of this) that has already been stated to achieve more on the density vertex of the process triangle than the performance or power ones. I'm not criticizing either of the processes, as a process is just a platform to build a product on. I'm just pointing out that thinking that the node jump from Intel7 to N3B is going to yield a processor that should clock to the stratosphere is a bit optimistic.

 

[Goop_reformed]

I'm just pointing out that thinking that the node jump from Intel7 to N3B is going to yield a processor that should clock to the stratosphere is a bit optimistic.

But it does give intel some leeway in terms of TDP/efficiency when their cores are already huge.

 

[LightningZ71]

Given the competitive environment that they exist in, they are effectively backed into a corner with respect to process/design tweaks. They HAVE to throw dump truck loads of transistors at their designs to achieve very high clocks. The HAVE to throw dump truck loads of transistors at their deigns to continue to push improvements in IPC. Cramming that may transistors into their cores means that they are forced to lean the process towards it's density maximums to hit those transistor counts. They also can't have too big of a frequency regression against their competition, so they have to push the performance corner. Both of those drag the efficiency corner down.

There's not a lot of places that they can go...

 

[dullard]

Lion Cove being +14% IPC vs Redwood Cove IPC is an estimate based on projections made by Intel.

Estimate is also tested, Intel always uses the term estimate and people don't get it.

Mikk is correct. Intel uses the label "estimate" because the products are not yet released and SPEC often requires that label. Below are the relevant SPEC reporting rules. Simply put, if a CPU is not generally available within 3 months of the first report of SPEC results, they must be labelled as an estimate. That doesn't mean the results are wrong. It just means that SPEC requires them to be labelled as an estimate because things often do change over time (updates to microcode, BIOS, Windows, etc all can easily impact results).

1.1. Purpose
Per the SPEC license agreement, all SPEC CPU 2017 results disclosed in public -- whether in writing or in verbal form -- must adhere to the SPEC CPU 2017 Run and Reporting Rules, or be clearly described as estimates.

https://www.spec.org/cpu2017/docs/runrules.html#rule_1.1

4.2. Systems not yet shipped
a. The component suppliers must have firm plans to make production versions of all components generally available, within 3 months of the first public release of the result.

https://www.spec.org/cpu2017/docs/runrules.html#rule_4.2

 

[dullard]

Why the wait? Arrowlake performance is already known at this time.

Why wait? We don't know final clocks (although the rumors are likely true), final microcode impacts, final price, final availability, final performance of iGPU and NPU, final performance at other power levels, and most relevant to the ST discussion: the final power used in ST usage.

 

[9949asd]

Intel literally published the data a month and a half ago, +14% over RWC that is marginally slower than RPC. +14% IPC at -8% clock speed compared to 14900KS. Where is the ST uplift supposed to come from?

Who will compare 285k to 149ks? Bro. That would be 285ks.

 

[adroc_thurston]

Who will compare 285k to 149ks? Bro. That would be 285ks.

2 bins of speed difference do not make.

 

[H433x0n]

Lion Cove being +14% IPC vs Redwood Cove IPC is an estimate based on projections made by Intel. It is not the same as AMD's official figures for Zen 5 vs Zen 4 of +16% which is based on internal testing on actual hardware.

In other words, the figure given by Intel is not comparable to the figure given by AMD.

View attachment 103801

You're right, the test suite they used is much better than what AMD presented for Zen 5 IPC calculation. If you used that same test suite to calculate IPC for Zen 5, who knows if you actually get a 16% average.