Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PPT1.jpg
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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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Exist50

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You don't expect a bigger gain with Arrow Lake? You think it will come with another low IPC increase over Meteor Lake?
Oh it will be better than RWC, but that's not exactly saying much. I'm expecting more like Intel's typical gains in the 10-20% ballpark, rather than 30%+. Though if we're comparing to MTL, they should get a frequency boost as well.
 

Geddagod

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If RWC+ has 10-12% more performance than RWC like Pat Gelsinger said then LNC will be much higher than that.
whispers maybe it's Lion Cove hmmmm
If Pat was talking about the core as in the core in the actual silicon and not the core vs core, node agnostically, then I think it's likely most of that 10-12% gain came from the node jump. Intel 3 to Intel 4 perf/watt gain is essentially the same as a standard node jump, and it's likely the perf/watt gain is going to be reflected in GNR much more than previous nodes due to the fact that since the core count is so high, each individual core is going to be clocked lower.
 

msj10

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whispers maybe it's Lion Cove hmmmm
If Pat was talking about the core as in the core in the actual silicon and not the core vs core, node agnostically, then I think it's likely most of that 10-12% gain came from the node jump. Intel 3 to Intel 4 perf/watt gain is essentially the same as a standard node jump, and it's likely the perf/watt gain is going to be reflected in GNR much more than previous nodes due to the fact that since the core count is so high, each individual core is going to be clocked lower.
he specifically mentioned that these 10-12% are on top of the 18% they get from the node jump

 

Geddagod

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he specifically mentioned that these 10-12% are on top of the 18% they get from the node jump

Huh you're right (I think). Ye I think it's getting more and more likely you are looking at LNC here. 10-12% is way too high for a "+" arch. At that point you are just reworking the core for a new arch. To put it into perspective, GLC is 15% better than ICL in server, LNC server being 10-12% better than RWC is server is a bit disappointing but plausible.
 

msj10

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Huh you're right (I think). Ye I think it's getting more and more likely you are looking at LNC here. 10-12% is way too high for a "+" arch. At that point you are just reworking the core for a new arch. To put it into perspective, GLC is 15% better than ICL in server, LNC server being 10-12% better than RWC is server is a bit disappointing but plausible.
maybe RWC+ is some kind of a RWC/LNC hybrid, they could have backported some of LNC features into it so it might not be as good as the final LNC we will see in LNL and ARL but it still gets a decent improvement but idk if something like that is possible.
 

DrMrLordX

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Tiger Lake H was better than Cezanne H in gaming laptops, you know, for gaming.

Eh? Maybe. It definitely was no match for Rembrandt in any case. And Rembrandt is in surplus mode as we speak. Intel isn't glutting the market with 4c Tiger Lake to compete performance-wise with Rembrandt, or even Cezanne.
 

eek2121

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Eh? Maybe. It definitely was no match for Rembrandt in any case. And Rembrandt is in surplus mode as we speak. Intel isn't glutting the market with 4c Tiger Lake to compete performance-wise with Rembrandt, or even Cezanne.
Tiger Lake was pretty close to Zen 3 in terms of IPC. Rembrandt does have the lead for most workloads and for power consumption, but the lead isn’t as big as you might think. Tiger Lake also had AVX-512. Rembrandt is on a superior process, so it has more room to stretch it’s legs.

Tiger Lake could have really shined for Intel if 10nm had worked out better. I was honestly surprised Intel didn’t shrink Tiger Lake and increase the core count to 10 cores while bumping frequencies for 12th gen, and I am surprised they are abandoning it so quickly.

IMO it was the closest Intel came to a balance of per/watt. Alder Lake blew everything up in terms of power consumption.
 
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I was honestly surprised Intel didn’t shrink Tiger Lake and increase the core count to 10 cores while bumping frequencies for 12th gen, and I am surprised they are abandoning it so quickly.
They couldn't contain their excitement to share E-cores with the world. Even with E-cores onboard, they managed to bungle up 12th gen mobile's power consumption. Only Intel can do that :D

They had another chance to deliver ADL-N with Intel 4 and take over the thin and light laptop market by storm with 20 hour battery life. Nope. Sensible thinking is outlawed in their offices.
 
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Ajay

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You are only fooling yourself if you believe that.

They've been doing it from day one in the Chromebook market.

Doesn't it strike you as odd that so few ARM based Chromebooks exist by comparison?

The reason is very simple - Intel priced most of the ARM vendors out of the market.

They might not be pricing as aggressively in periods where no ARM vendors are making an effort, but you can bet that they are doing it the moment Qualcomm or Mediatek start making announcements to that effect.

This is especially obvious given the fact that Chrome OS supports Android apps which overwhelmingly work better on ARM CPUs due to ARM's near total dominance of the Android device market.
Unless I misunderstood the recent quarterly report, there was no contra revenue. Intel did cut ASPs drastically in many areas, but that’s not quite the same, IMHO.
 

Geddagod

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View attachment 80468

Interesting pic of Lunar Lake showing the layout of the cores.
Hah. The twitter user who leaked this a month? or two ago deleted this in the comment thread he originally posted it. IIRC he said he got it from chiphell? Again, doubt it's fake though.
I'm assuming this is a thermal test platform for early, early silicon of LNL (on TSMC 3nm, come at me A/// lol) . Apparently the 'compute' tile on LNL contains a lot more than just the CPU cores- iGPU, LP cores, and SLC.
The picture doesn't tell you a lot (other than confirming the 4+4 config), and I think the E-cores this time around will actually be used like how Apple uses their small cores, turning them on for idle and low power tasks as to not bother the big cores, and being able to isolate the cores much better than what Intel does with big.little on laptops right now.
As in Intel might not need to include a 'low power island' on the soc tile with LNL to preserve battery life.
Just for kicks and giggles if anyone cares, the 4 big cores on this picture *very inaccurate due to it looking like thermal testing with no clear boundaries* is ~28mm^2 IIRC (did the math a while ago and rn I'm stressed about my math test tmmrw lol).
That's also not too far off from what a RWC 4C complex with L3 would be. So despite being a node shrink, being around the same area implies bigger cores or more cache, aka higher ipc/better efficiency.
 

msj10

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Just for kicks and giggles if anyone cares, the 4 big cores on this picture *very inaccurate due to it looking like thermal testing with no clear boundaries* is ~28mm^2 IIRC (did the math a while ago and rn I'm stressed about my math test tmmrw lol).
the P-core looks smaller to me relative to the E-cores than RWC or GLC was but like you said it's very difficult to draw any conclusions from this.
 

Geddagod

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the P-core looks smaller to me relative to the E-cores than RWC or GLC was but like you said it's very difficult to draw any conclusions from this.
I think finding the P-core itself is pretty much impossible to find the size of from this pic. My 28mm^2 estimation was the entire 4C cluster, as in core, L2, L3, ringbus, the works. Pretty much just that giant top rectangle with all 4 big cores in it, with the 17.4mm line as scale.
The reason I said it looks similar size to RWC was, from a quick discord search from a server I'm on lol, 8RWC+24MB L3 = 63mm^2, half of that would be ~30, around the same as a 4C LNC cluster according to the pic.
A node shrink + new arch usually results in the new core being 60-80% the size of the previous one (sandy bridge vs haswell, haswell vs skylake, skylake vs sunny cove). I don't think LNC is going to be much different, though I will say the trend of the next arch+node core shrinking has been a slowly dying trend it looks like.
 

Geddagod

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I do want to add something kinda weird about that pic tho, if it is a thermal image...
Why does it look like the decode/load/store were the hottest parts of the core? Isn't GLC's decoder clock gated like 80% of the time? I always assumed that honor went to the FPU.
And where is the adjacent L3 slice for the little cores?
 

msj10

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I think finding the P-core itself is pretty much impossible to find the size of from this pic. My 28mm^2 estimation was the entire 4C cluster, as in core, L2, L3, ringbus, the works. Pretty much just that giant top rectangle with all 4 big cores in it, with the 17.4mm line as scale.
The reason I said it looks similar size to RWC was, from a quick discord search from a server I'm on lol, 8RWC+24MB L3 = 63mm^2, half of that would be ~30, around the same as a 4C LNC cluster according to the pic.
A node shrink + new arch usually results in the new core being 60-80% the size of the previous one (sandy bridge vs haswell, haswell vs skylake, skylake vs sunny cove). I don't think LNC is going to be much different, though I will say the trend of the next arch+node core shrinking has been a slowly dying trend it looks like.
I am not disagreeing that it can be a similar size to RWC, I am saying that relative to the E-cores it looks smaller, that could be because Skymont got bigger.
 
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Geddagod

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Redwood cove looks like golden cove supercharged.. l2 structure
Waiting for Tom to explain to his viewers how Intel engineers thought the relatively minor changes in RWC vs GLC was going to cause a 20% IPC gain.
Full disclaimer, I'm no chip architect, but to me crestmont looks like it saw more/bigger architectural changes vs gracemont than rwc did vs glc. While there is no specific bottleneck breakdown for GRC, for modern cores isn't the front end almost always the bottleneck? And wasn't the renamer in most archs (and GRC too I'm pretty sure) the limit to max theoretical ipc to the core as well?
The RWC L1 changes look interesting, but I suspect that it would add extra cycle(s) of latency, limiting performance benefit. Perhaps they did it for efficiency and to better feed their wide decoders, idk. I do think it's interesting though, AMD has very large uOP caches while Intel looks to be going wide decode + larger caches in order to feed the rest of the core.
 

Henry swagger

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Waiting for Tom to explain to his viewers how Intel engineers thought the relatively minor changes in RWC vs GLC was going to cause a 20% IPC gain.
Full disclaimer, I'm no chip architect, but to me crestmont looks like it saw more/bigger architectural changes vs gracemont than rwc did vs glc. While there is no specific bottleneck breakdown for GRC, for modern cores isn't the front end almost always the bottleneck? And wasn't the renamer in most archs (and GRC too I'm pretty sure) the limit to max theoretical ipc to the core as well?
The RWC L1 changes look interesting, but I suspect that it would add extra cycle(s) of latency, limiting performance benefit. Perhaps they did it for efficiency and to better feed their wide decoders, idk. I do think it's interesting though, AMD has very large uOP caches while Intel looks to be going wide decode + larger caches in order to feed the rest of the core.
Redwood cove will have even more l1 bandwidth.. the old leaks mention that.. yeah i think crestmont will have big ipc if they increase the robs to 320+ .. they.l reach rocket lake zen 3 ipc 😃
 

Exist50

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Isn't GLC's decoder clock gated like 80% of the time? I always assumed that honor went to the FPU.
I think the OOO is typically a hotspot. Maybe the FPU if you're running a power virus, but we don't know the workload in question here. Also, if we're ever to see a fundamental relayout of the core, it would be with Lion Cove, so mapping to particular structures is likely impossible without more information.
 
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A///

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that would depend on intel and microsoft working on the scheduler so it behaves as apple does it or else it'll be a sliding scale of how accurately it assigns tasks.

I'm assuming this is a thermal test platform for early, early silicon of LNL (on TSMC 3nm, come at me A/// lol) . Apparently the 'compute' tile on LNL contains a lot more than just the CPU cores- iGPU, LP cores, and SLC
Got my club ready but would rather a cinder block. you'll get your atta boy when a product comes out on that node.
 
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