Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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A///

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there is an added benefit to a larger socket size for both intel and amd if they both went that direction to hold more compute chiplets if you think about it, more complex install be damned.
 

deasd

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I don't remember you saying the same when AMD chose not to support it for years.

Please do explain how Intel disabling AVX-512 on a fraction of Intel CPUs deprives AMD users of that feature? No mainstream use case was ever going to design around the ADL 6+0 die in particular.

And sooner or later, this will be solved. No way Intel's going to waste all the software effort they put into AVX-512. Either they'll bring it to E-cores, or define 256b versions of the new ops. Though I wouldn't be surprised if that takes till after Skymont.
i don't see major software ever utilising the power of avx512 and thus it feels like amd wasted silicon space on something that isn't going to be worth for maybe 98% of their consumers for mainstream desktop. I'd like to be proven wrong by hard statistics but I firmly believe only 2% utilise avx512 for scientific workloads discounting any hobbyist folding regime.

Maybe some application just start using avx512 while guys don't realize? In Zen4 review TPU tested Ryujinx emulator with avx512 patches from last year,



AI learning like Topaz Gigapixel also has great boost when utilizing avx512, some old data like 11900k didn't have that boost due to older version being used in old review.



ai-upscale.png


and the way amd implementing AVX512 is to use existed dual 256bit pipeline that has no space waste which is clever move. But Intel side use 512bit pipeline inside P cores while leave E cores with even no native 256bit pipeline support which mess up the avx512 support.
 
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I don't remember you saying the same when AMD chose not to support it for years.
They had better things to do at the time. Like kicking Intel's behind with Threadripper and Zen 3 :D

I'm more furious that Intel took away an option that they provided at ADL launch. That's the stupidest decision ever and could only be made by a dumb executive.

Keep the option in BIOS and make it as obscure as possible to dissuade people from using it. I think they got more concerned that people were turning off E-cores to keep AVX-512 active and to avoid hetereogenous core shenanigans. They basically forced everyone to taste their E-cores, like bitter medicine.
 
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A///

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not for intel or amd but I'd rather use puget's benches than tpu. emulators are great but the market for them is small. ime most people who use topaz or similar daily are running much higher end systems than flagship mainstream where avx512 already exists.


I'm not sure most hobbyists are using topaz's products daily for this to matter in the extent which you are attempting to portray it as but topaz carries a high sales price and a high renewal fee, each coming with one year of ugrades otherwise you can buy once with a year of upgrades and keep that version forever missing out on new features.
 
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eek2121

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It's not that I don't think they can it's that I don't see the cost vs benefit basis of it. Crestmont, which comes after Gracemont, is not expected to have AVX512 either. For Intel the time and energy spent implementing AVX512 on both p and e cores and making sure they communicate with the OS without hiccup under Linux or Windows is a large money and time glut when they can not include AVX512. If I had to pull a number out of my rear I'd say less than 2% of general consumers benefit from AVX512. My understanding is the benefit general consumers will see from AVX512 is in retro game emulation which can't be discussed at length due to it being gray area piracy.
AI is going to become a not-insignificant part of client computing in the future. AVX-512 helps accelerate certain things related to AI. Therefore, if Intel wants to be a part of the future they need to get on board.


I would believe that, except Intel launched Alder Lake with AVX-512 enabling option in BIOS. Then backtracked due to some order from a high ranking executive (no idea who). Dr. Ian reported that the engineers who had worked on AVX-512 on ADL were taken aback and pissed when they learned that AVX-512 was getting disabled post launch. It makes no sense to take AVX-512 away, just to make your puny cores work. It feels like they forced their decision down everyone's throats and took an option away from enthusiasts while also making their CPU look lacking compared to Zen 4.
Intel pulls stuff like this all the time. Intel and AMD often have unused, incomplete, or obsolete settings exposed via the UEFI. It has nothing to do with being rush.
 

Kocicak

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I'm more furious that Intel took away an option that they provided at ADL launch. That's the stupidest decision ever and could only be made by a dumb executive.
...
They basically forced everyone to taste their E-cores, like bitter medicine.
You cannot support a feature that melts your products.

Almost everybody loves E-cores. And who does not just needs some more time to understand.
 
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A///

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AI is going to become a not-insignificant part of client computing in the future. AVX-512 helps accelerate certain things related to AI. Therefore, if Intel wants to be a part of the future they need to get on board.
For client side you're better off leveraging the igpu or gpu for those simd instructions. Then there's all the xilinx ip that would allow amd to bypass all of that noise in the first place, altera for Intel. Not long ago it didn't make sense to implement those in a client side processor because why was the main reason and cost being a significant factor. Time passes it gets cheaper. It took apple to show them all it was a viable direction. avx512 is not some magical bean you jacked from jack's palm when he wasn't looking. There are more efficient avenues to increase performance. Expect some major changes in x86 design beginning a few generations from now. avx512 as popular as it is now will take a back seat by then.
 

A///

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Almost everybody loves E-cores. And who does not just needs some more time to understand.
i myself thought it was stupid until I had some personal time with a 12 gen system which sounds very wrong when I phrase it like that but in my limited testing with a 16 core 12 gen it operates nicely if you minimise an active project only to see the processing get handed off and you can play a game or work on another project up front without any issues. core control should get better over time due to windows updates and better scheduling. you can't one and done it like most people assume.
 

ondma

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Progress has taken a step back because of Intel's bone headed decision. AMD added AVX-512 so developers had an incentive to explore it further for use in their software since they wouldn't have to worry about implementing a feature only for Intel users and not AMD users. But now they won't explore using this feature coz the latest Intel CPUs don't have it anymore. When's the last time some developer went out of their way to make something run better on AMD CPUs? Intel disabled the BIOS option on purpose. If they can't have it, they won't let AMD enjoy it either. They know the majority of developers think Intel first AMD second.
Or maybe it is simply because their cpus run hot and use too much power already. Naw, that would be too simple. Much better to infer some malicious motive. Lots of projection in this post, young Padawan.
 

Exist50

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Maybe some application just start using avx512 while guys don't realize? In Zen4 review TPU tested Ryujinx emulator with avx512 patches from last year,



AI learning like Topaz Gigapixel also has great boost when utilizing avx512, some old data like 11900k didn't have that boost due to older version being used in old review.



View attachment 79437


and the way amd implementing AVX512 is to use existed dual 256bit pipeline that has no space waste which is clever move. But Intel side use 512bit pipeline inside P cores while leave E cores with even no native 256bit pipeline support which mess up the avx512 support.
AVX-512 certainly has some meaningful and valid use cases, but the suggestion was that Intel should abandon hybrid in order to support it. That seems like a losing tradeoff in the vast majority of cases.
 
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A///

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Getting HT to work on the e cores, imho, is a lot more important than avx512, especially as intel plans based on rumors, to leverage altera among other acquisitionary ip into their future hardware. avx512 while legitimate and having a use has sadly become a buzzword in consumer computing and I'm exaggerating its commonality there.
 

Hulk

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Getting HT to work on the e cores, imho, is a lot more important than avx512, especially as intel plans based on rumors, to leverage altera among other acquisitionary ip into their future hardware. avx512 while legitimate and having a use has sadly become a buzzword in consumer computing and I'm exaggerating its commonality there.
I asked IntelUser2000 about adding HT to the E cores a while back and he said something to the effect that they weren't designed with HT in mind and it won't happen.
 
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I'm thinking Intel will release (or announce) 14th gen MTL mobile CPUs (U-series) this year and also 14th gen desktop CPUs based on RPL refresh. Is there any reason to think RPL refresh will be called 13th gen instead? Coffee Lake Refresh was called 9th gen so I think history will be repeated.
 

A///

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I asked IntelUser2000 about adding HT to the E cores a while back and he said something to the effect that they weren't designed with HT in mind and it won't happen.

Those are some dire claims. Intel for the last five or six years now has found itself with its pants down. If rumors resolve and AMD does incorporate smaller cores into their mainstream design and those are SMT while offering a wide gap in performance, less power usage and better thermals Intel will be slow to react. The point I'm attempting to drive home is Intel has decided and claimed many talking points in the past only to go back on them or done as they spoke against.

I wouldn't say Intel will bring it, but I also wouldn't say they wouldn't ever bring it or haven't entertained the idea and kept it under wraps. Is Intel going to take the proverbial pole from AMD for another five to six years while their entire product stack gets outclassed by their smaller competitor? Intel can only add on so many e cores before it becomes a drain on resources and affects stability for the end user, and they're more limited with p cores. AMD isn't in the clear either.

Fun surprises indeed.
 

A///

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I'm thinking Intel will release (or announce) 14th gen MTL mobile CPUs (U-series) this year and also 14th gen desktop CPUs based on RPL refresh. Is there any reason to think RPL refresh will be called 13th gen instead? Coffee Lake Refresh was called 9th gen so I think history will be repeated.
8th to 9th was very different. The core and thread count changed quite a bit. I don't recall if it was down to fusing off or a design change. I can see why your mind is going to that because of the naming rumor article from a few days ago. The only semi confirmed change is larger cache. Intel could name it the 13950K to troll AMD. The MTL processors will have L4 but that L4 is blocked off from the igpu from what I saw this morning. MTL ARL are the two most confusing releases because they've been discussed at length for a long time without any concrete info.
 
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uzzi38

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Or maybe it is simply because their cpus run hot and use too much power already. Naw, that would be too simple. Much better to infer some malicious motive. Lots of projection in this post, young Padawan.
AVX-512 was not the thing that was going to push it over the edge, especially not when you had to disable all the e-cores in order to use it.

Those e-cores aren't exactly free for power usage.

Besides, Intel's client implementation of AVX-512 is also 2x256b afaik, and we saw on ICL and TGL that it didn't have that significant of an impact on power. It's just a shame the option is gone. The malicious motives are unnecessary and I agree with you on that point, but the overall complaint of AVX-512 being removed I think is still valid.
 
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I can see why your mind is going to that because of the naming rumor article from a few days ago.

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Hadn't seen that rumor but it seems to confirm that Intel is VERY predictable. They don't want to explain to investors, I guess, about why a year later they are releasing 13th gen refresh parts so they just call them 14th gen and pretend that they made a gen worth of progress.
 
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Hulk

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View attachment 79480

Hadn't seen that rumor but it seems to confirm that Intel is VERY predictable. They don't want to explain to investors, I guess, about why a year later they are releasing 13th gen refresh parts so they just call them 14th gen and pretend that they made a gen worth of progress.

Raptor Lake Refresh

Past history shows Intel to have progressed from one generation to the next using at least one of the following.

1. New architecture - Lots of examples of this but we can look at Comet Lake to Rocket Lake as an example of keeping the same node and advancing architecture. What we used to call a "tock."
2. New process, what we used to call a "tick."
3. Increase core count ie Coffee Lake Refresh.
4. Increase clocks ie Kaby Lake Refresh.

Now the dilemma Intel sees itself in now is that Raptor Lake is already a refresh of Alder Lake, have increased increased core count and frequency, points 3 and 4 above. New architecture and new process are also off the table so the question is how to refresh a refresh for Intel?
 

Hulk

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Remember Comet Lake? Okay, imagine that if it had only been 8c instead of 10c. There you go.
You are right in that Coffee Lake Refresh to Comet Lake was one of the weakest "new" generations from Intel and probably an apt comparison to what we can expect for the Raptor Refresh.

Comet Lake brought die thinning, thermal velocity boost, favored cores, and about 300MHz clock increase, along with 10 cores at the top of the stack.

Remove the 10c and Comet was basically Coffee Lake.

The problem still remain for Intel in that it is unlikely they will be able to add cores OR increase clocks higher than the current 6GHz.
 

Geddagod

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Getting HT to work on the e cores, imho, is a lot more important than avx512, especially as intel plans based on rumors, to leverage altera among other acquisitionary ip into their future hardware. avx512 while legitimate and having a use has sadly become a buzzword in consumer computing and I'm exaggerating its commonality there.
HT costs a 5% die area overhead and results in a 15-30% performance benefit in common MT applications according to Intel.
However this might not apply as much to the E-cores due to the shorter pipelines and lower ability to gain extra ILP from SMT. Plus I'm assuming there's a cost overhead involved.
I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.
 
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I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.

Intel states that it has a Resource Director that will arbitrate cache accesses between the four cores in a cluster to ensure fairness, confirming that Intel are building these E-cores in for multi-threaded performance rather than latency sensitive scenarios where one thread might have priority.
So if they increase the thread account with SMT, each thread will have to wait longer for cache access and it will also reduce the amount of data each thread can keep in the cache before it gets evicted, necessitating an increase in cache size. So maybe that's why they had to double the E-core cluster cache size in Raptor Lake to ensure that the extra E-cores don't sit idle for too long waiting on the cache. They might be able to put in SMT in the E-core cluster but then they may need to increase the shared cache to 6 or 8MB.

The Resource Director is what's bad for E-core threads needing the full amount of the cache, like some critical game engine thread coz the RD will regularly slap it to release its clutches from the cache and let the other threads have their fair share. The E-cores are meant more for workloads where all the threads play well together.

(Feel free to poke holes in my wild theory :D)
 
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naukkis

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HT costs a 5% die area overhead and results in a 15-30% performance benefit in common MT applications according to Intel.
However this might not apply as much to the E-cores due to the shorter pipelines and lower ability to gain extra ILP from SMT. Plus I'm assuming there's a cost overhead involved.
I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.

HT basically cuts per core performance to half. It's pretty much opposite what they actually want for hybrid designs - so instead of adding SMT to E-core Intel should get rid of SMT from P-cores too as halving P-cores per thread performance with SMT is basically just opposite what P-cores are supposed to do - increase per thread performance. SMT makes sense for low-core count desktop/mobile solutions - but high core count cpu's should get rid of it.