Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

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Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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Geddagod

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Let's see Raptor refresh is coming by end of September whatever the final specs are on it. MTL mobile comes out sometime this year or next. I want to say there has been a year or two where Intel didn't release a major platform and it was pushed way to the end and launching early next year. A health intel firing on all pots would have released 2 major milestones in a year like they have a few times in the past. Arrowlake based on rumors I've read and been posted here uses a new approach to the design based on the Intel engineering day of 2020 or 2021... anyway it's a lot for a first generation product. the backside power delivery is a new feature but as is their new transistor tech. It's a lot on their plate. My only other guess is they do what you said but they're producing right now and testing long term to address issues. mtl es are in the wild as of 2 days ago. still no clue when they'd launch but if arrowlake is to follow those es and es leaks will be gold for anyone who can get their hands on them with the dev board or the prelim data. getting all this right is essential for Intel to catch up or lose more if they fail.
Backside power delivery is being tested on Intel 3 before Intel 20A. Idk what they mean by "internal node". Maybe they just have it in labs with no products using it?
I don't think ARL's structure is going to differ from MTL's, nothing like multiple compute tiles or anything imo. Jim thinks there's going to be 3D stacked cache somewhere on it though, but honestly I think if it is there, it's going to be cache on the interposer, which I believe? Intel tried with Ponte Vechio.
 

Saylick

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Internal Intel 3 node for backside power delivery, officially Intel 20A for both, prob going to in ARL. It seems to be pretty much impossible for Intel 20A to be out 2024, unless its at the very end of 2024 as a paper launch. Offc Intel could decide not to implement it in ARL too I assume, to derisk the development
If they remove backside PD from 20A, as a means of derisking, then to me it sounds like they're admitting their schedule was too aggressive. The whole point of that internal Intel 3 node was to get BSPD working.
 
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Geddagod

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I don't mean to derail the thread but to answer your question, I think Nvidia will delay moving to MCM, chiplets, or some form of advanced packaging for as long as possible. They'll start with their server hardware in the form of COPA, then if there's even a desire for it, they'll transition the top SKU (i.e. xx100 or xx102 class dies) as the flagship xx90 and xx90 Ti to the consumer side. Anything less than that can remain monolithic. MLID speculated that Nvidia might not even care in the near future that their top consumer SKU isn't some >500mm2 honking GPU because their game plan is to just win via software features, not raw horsepower outright. That, along the fact that they much prefer the margins in the enterprise space, means consumers are valued less and less to them moving forward.
Ye I doubt that. Software can only do so much, especially for consumers who mostly just want traditional raw raster and maybe some RT mixed in. I'm not discounting a potential architectural advantage that may allow Nvidia to be more efficient in perf/area, but short of a radical improvement in consumer related software...
And doesn't Nvidia still make a killing from consumer GPUs? I doubt they discontinue their top skus. I agree they will delay chiplets as long as possible, but I don't think MLID is right with what he thinks Nvidia's plan is for consumer GPUs
 

A///

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Backside power delivery is being tested on Intel 3 before Intel 20A. Idk what they mean by "internal node". Maybe they just have it in labs with no products using it?
I don't think ARL's structure is going to differ from MTL's, nothing like multiple compute tiles or anything imo. Jim thinks there's going to be 3D stacked cache somewhere on it though, but honestly I think if it is there, it's going to be cache on the interposer, which I believe? Intel tried with Ponte Vechio.
It means they're dog fooding their product.
 

Geddagod

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If they remove backside PD from 20A, as a means of derisking, then to me it sounds like they're admitting their schedule was too aggressive. The whole point of that internal Intel 3 node was to get BSPD working.
Ye I agree. This is just conjecture though, I wanted to stress the point that just because Intel is technically capable of using a ton of new stuff in ARL, they might not in order to not risk too much.
 

mikk

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The article you are quoting from agrees that Intel 18A would use High NA if it comes out in time.
The quote you chose from the article doesn't show the full picture- here's some more context


No they don't, you have to read further. To help you out:

While Intel's 18A technology would greatly benefit from High-NA EUV tools, it looks like Intel does not necessarily need Twinscan EXE:5200 machines for this node. Usage of multi-patterning for commercial chips means a longer product cycle, lower productivity, higher risks, and potentially lower yields (though the latter is not cast in stone). Yet, it looks like Intel wants its 18A node to arrive as soon as possible, perhaps because it considers it a major tool that will allow it to recapture process technology leadership from TSMC. Consequently, Intel's updated plans are now to phase in High-NA tooling during 18A's lifecycle if the tools are completed on time.


What you are quoting is the old outdated assumption from 2021 which they repeated. And this is just an assumption from Anandtech, Intel never claimed 18A will be using High-NA. If you can prove that 18A will be using High-NA you should do it but make sure this is a source from Intel, Anandtech is just messy in this regards.
 

Geddagod

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No they don't, you have to read further. To help you out:




What you are quoting is the old outdated assumption from 2021 which they repeated. And this is just an assumption from Anandtech, Intel never claimed 18A will be using High-NA. If you can prove that 18A will be using High-NA you should do it but make sure this is a source from Intel, Anandtech is just messy in this regards.
I included that quote in my previous comment.
I don't think it's an assumption. This is cited not only by Anandtech, but semiengineering, and many other reporters as well.

Intel 18A products are going to be HVM in 2025. That's from Intel themselves. Clearwater forest, on Intel 18A, perfectly fits that timeline. Do you think Intel is going to have Intel 16A products in HVM in 2025? Because that's the only other node Intel could be talking about for high NA EUV.

Ann claims their nodes have high NA and non-high NA EUV versions in order to safeguard against delays. Now, they not be referencing to Intel 18A like you think. However that doesn't make much sense because this claim was before the announcement that Intel 18A got pushed to 2H 2024. The 2025 node they were almost certainly referencing was Intel 18A.

Ann claims they will put high NA into use as soon as they get the machines up and running, and the only way this makes sense is if Intel 18A was compatible with high NA. Especially when you consider that Ian asked if they could put high NA EUV earlier than expected, Ann still answered yes. So even if she was talking about Intel 16A, it kinda confirms Intel 18A is still compatible since it's the node directly before it

However, maybe I interpreted Ann wrong as well. I'll admit this is very ambiguous and I certainly never try to argue I can't ever be wrong.
 

mikk

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I included that quote in my previous comment.
I don't think it's an assumption. This is cited not only by Anandtech, but semiengineering, and many other reporters as well.


Then feel free to prove it. Even Anandtech does not believe in it, did you see their updated roadmap? You also keep ignoring the only Intel source where all nodes up to 18A are said to use regular EUV. This is the only Intel source, why do you ignore that? Don't you think the slide would look a bit different if Intel thought High-NA is a realistic option for 18A? You keep arguing with a quote from 2021 while you keep ignoring the newer Intel source from 2022.

From IEDM in late 2022

Nothing about High-NA. Intel 18A manufacturing ready in H2 2024 does not agree with High-NA. Too late and risky, this is something for a future node after 18A.
 
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Geddagod

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Then feel free to prove it. Even Anandtech does not believe in it, did you see their updated roadmap? You also keep ignoring the only Intel source where all nodes up to 18A are said to use regular EUV. This is the only Intel source, why do you ignore that? Don't you think the slide would look a bit different if Intel thought High-NA is a realistic option for 18A? You keep arguing with a quote from 2021 while you keep ignoring the newer Intel source from 2022.

From IEDM in late 2022

Nothing about High-NA. Intel 18A manufacturing ready in H2 2024 does not agree with High-NA. Too late and risky, this is something for a future node after 18A.
I literarily just proved it. Unless you think Intel 16A is going to be in HVM in 2025, the only node Intel could be talking about HVM is Intel 18A. This is from your own slide, it says HVM in 2025 for High NA EUV.
Ananadtech DOES believe it. Idk if you read the article you posted but, it literally states
Consequently, Intel's updated plans are now to phase in High-NA tooling during 18A's lifecycle if the tools are completed on time.
I'm not ignoring that source. I'm saying Intel 18A uses BOTH High-NA tooling and regular EUV. Regular EUV is to be used first, and high NA if they get the tools out on time.
This is what Ann implies too, when she says whenever High NA is available they will use it, because their nodes are designed for BOTH High NA and regular EUV.
The slide would not look different, because Intel has been very dodgy on where they will use High NA. Based on their terrible history of node announcements, relatively new work with EUV, and ASML having issues with High NA EUV, I don't think Intel wants to make a specific commitment to the public about where High NA is going to be used. You wonder why Intel keeps on telling us why they will keep on using High NA whenever they can?
Are you just ignoring Ann saying that Intel 18A is developed for both High NA and regular EUV?
Are you just ignoring that this interview was from 2022 not 2021?
Are you just ignoring that if the only evidence I had was from that 2021 article than I wouldn't have been able to say that Intel 18A also had regular EUV designs all the way from my first comment about High NA?
IIRC Intel 18A is also designed for using regular EUV machines too, as a safeguard against delays
And a realistic option for Intel 18A? If anything, High NA EUV would be easier to develop, since they probably would get to avoid more multi-patterning techniques with High NA.
Oh and cmon, literally everything I see online seems to indicate that High NA EUV would be used (even if it's not initially) for Intel 18A. Redfire, semiengineering, TWO different authors on Anandtech.... what I'm suggesting isn't some far off conspiracy theory lmao.
We know Intel has designs for high NA EUV for 18A. We know Intel is going to use high NA EUV for HVM in 2025. We know Intel is going to use high NA EUV as soon as the machine is ready, note, not as soon as the node is ready, since high NA EUV is node agnostic according to Ann herself, and that's crossing paths exactly for when Intel 18A is entering HVM manufacturing- 2025- for Clearwater Forest. That's the proof. Idk why you simply choose to ignore this.
 

Exist50

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If they remove backside PD from 20A, as a means of derisking, then to me it sounds like they're admitting their schedule was too aggressive. The whole point of that internal Intel 3 node was to get BSPD working.
There's no chance they remove backside PD at this point. Redefining the whole metal stack? You're basically talking about an entirely different node.
 
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A///

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I had a good laugh earlier when I read his post saying "backside PD" not the wisest word combination.:laughing:

can someone please post a screen shot of this komachukarus twitter so I can see what he said about the igpu on mtl es hitting 2 ghz?
 

Geddagod

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I had a good laugh earlier when I read his post saying "backside PD" not the wisest word combination.:laughing:

can someone please post a screen shot of this komachukarus twitter so I can see what he said about the igpu on mtl es hitting 2 ghz?
I don't have access to it either. I heard it from Bionic Squash on the C&C discord server. 2.1Ghz peak actually. You could request access from Komachi's twitter, or DM Bionic Squash ¯\_(ツ)_/¯
 

mikk

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I literarily just proved it.

No you don't and you cannot. There is no source from Intel where they confirmed 18A is using High-NA, it's the opposite. Also H2 2024 manufacturing ready doesn't match with the readiness of High-NA. This is how wrong speculations emerge by the way.
 

Geddagod

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No you don't and you cannot. There is no source from Intel where they confirmed 18A is using High-NA, it's the opposite. Also H2 2024 manufacturing ready doesn't match with the readiness of High-NA. This is how wrong speculations emerge by the way.
H2 2024 manufacturing ready. Intel 18A is launching in 2025 for Clear Water forest, and will ramp throughout the year. Do you think Intel 16A will be in HVM in 2025 then?
 

msj10

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Hulk

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Meteor Lake will have an L4 cache die?

At first glance this looks like a return to "Crystal Well" to support the rumored increased iGPU performance of Meteor Lake.

But there is probably more to it as Intel it seems has been trying to optimize cache structure as core counts increase and they move to a tiled format. Will they continue to go with a shared L3 like SPR for all cores or will they eventually move to L3 desegrated to clusters of cores aka AMD Zen? We know that there is quite a latency penalty when Golden Cove reaches for L3 and that's probably why it was important to increase L2 in Raptor Cove in order to mitigate that effect.
 

Exist50

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Bad sign. 14th gen (RPL-Refresh and MTL)seems to be a longer peroid product than previous speculation, it include RPL-S, HX, and MTL which are low power SKUs only. This would be another 'Coffeelake+Cannonlake' situation until full-lineup Arrowlake arrive.

The HX line has used desktop silicon since Day 1. Not really a surprise.