Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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DavidC1

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I mean they have deep insight into their product and iterate over it. Do you really believe that the tiles stay the same ? Look at Gaudi, Xeon and the current Lunar Lake. They went full in on tiles, learned a lesson and are now reducing them and using them more efficiently.
Which isn't Arrowlake. Yea they can do better, but within the insanity of having four tiles arbitrarily separated basically.

Let me tell you what the modern "Conroe" and "Athlon 64" is. It's Apple's M1.
 

AcrosTinus

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It might be faster but it's MTL with minimal changes except in the compute Tile. I agree it can be better but MTL's deficiency needs to be overcome FIRST before they can imagine faster than the sane design called Lunarlake.
Where do you get this from, I found nothing that even relates MTL to ARL.
If I look at the current development, since the introduction of the tiles, they never really stayed the same.
 

DavidC1

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Where do you get this from, I found nothing that even relates MTL to ARL.
If I look at the current development, since the introduction of the tiles, they never really stayed the same be it on server or gaudi.
If you don't know this then the discussion is pretty much over. I suggest you look at leaks and former Intel presentations. No more "Oh I think" which means for a newcomer is essentially "in my head".
 

AcrosTinus

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If you don't know this then the discussion is pretty much over. I suggest you look at leaks and former Intel presentations. No more "Oh I think" which means for a newcomer is essentially "in my head".
Very friendly reply, I'll read into it.
The official reveal of the product is quite near and we will see :)
 

TwistedAndy

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I am not sure why you think Arrowlake will use a different approach when it's basically Meteorlake with different tiles. GPU being based on ACM is a proof of that. So you are saying that ARL will have a IMC on compute tile AND disabled one on the SoC Tile?

I have found a slide from Intel:

22_intel_arrow_lake_s_ma_podobno_powstac_w_litografii_tsmc_n3_podczas_gdy_arrow_lake_p_skorzys...png

It looks like Arrow Lake will have a similar structure to Meteor Lake, with an NOC, a separated memory controller, and other stuff (aka the new approach).

SLC is the same approach for Apple parts, to lower power. Their problem was their IO(the chipset) had higher power. By having trivial data(compared to compute requirements) in SRAM, it saves an enormous amount of power. Power savings first, then performance.

Yes. Meteor Lake suffered a problem when two LP E-cores weren't powerful enough to perform most of the light tasks. As a result, the CPU tile was used much more frequently. Having that in place decreases the power consumption.
 

DavidC1

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I have found a slide from Intel:

View attachment 102155

It looks like Arrow Lake will have a similar structure to Meteor Lake, with an NOC, a separated memory controller, and other stuff (aka the new approach).
No indication that it uses a separate memory controller. This is just a hopeful guess right? The whole point of the hodgepodge four tile config is so they can change one at a time as needed at a different time. If they are changing where the IMC is then they have to change the SoC Tile as well, and how all the blocks within work and communicate with each other.

The presentation shows that they aren't even changing the Foveros size for Arrowlake and remains at 36um. Meteorlake is the System Change and Arrowlake is the Core Change.

GPU using ACM++ is an example. Apparently based on the results it's not working as well as they expected. And what are they going to do by having four different tiles? Do a 3 month refresh? They aren't going to do that. It's still 1 year.
Yes. Meteor Lake suffered a problem when two LP E-cores weren't powerful enough to perform most of the light tasks. As a result, the CPU tile was used much more frequently. Having that in place decreases the power consumption.
Not just that. The E cores are on a very high performance ring bus. Buses are the LAST agent to get idle, because it's what's common among the cores. If one measly E core wants communication, then the ring has to be on. This means buses and IO are the floor to how low you can go low in power.

Lunarlake puts them on a separate much slower bus for the same reason, optimized for power efficiency. Thus Lunarlake simplifies the setup, reduces complexity and thus execution issues, improves performance, saves space, and lowers power.
 
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TwistedAndy

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No indication that it uses a separate memory controller. This is just a hopeful guess right? The whole point of the hodgepodge four tile config is so they can change one at a time as needed at a different time. If they are changing where the IMC is then they have to change the SoC Tile as well, and how all the blocks within work and communicate with each other.

With the tiled approach, Intel has to separate the memory controller and put it into the SoC tile, as we have in Meteor Lake. There are no other options. Intel will probably also put some hidden LP E-cores in the Arrow Lake SoC tile. At least it makes sense for ARL-H and even HX.

I was considering an option when the whole CPU is monolithic. In this case, it makes sense to use the old approach with the ring and a memory controller on it.

The E cores are on a very high performance ring bus. Buses are the LAST agent to get idle, because it's what's common among the cores. If one measly E core wants communication, then the ring has to be on. This means buses and IO are the floor to how low you can go low in power.

Yep, and that's why we have those cores in the SoC tile :)
 

DavidC1

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With the tiled approach, Intel has to separate the memory controller and put it into the SoC tile, as we have in Meteor Lake. There are no other options. Intel will probably also put some hidden LP E-cores in the Arrow Lake SoC tile. At least it makes sense for ARL-H and even HX.
They aren't doing that in Arrowlake which is the point. It's still four tiles. Pantherlake, Novalake, Anandlake, or Twisted Andylake can do whatever, but not in Arrowlake without changing both tiles significantly.
Yep, and that's why we have those cores in the SoC tile :)
No, on Lunarlake it's on the compute tile. On Meteorlake it basically doesn't work. It is pretty looking at the die, but that's about it. It literally sits there pretty. Intel themselves said it saves a mere 150mW! My efficient Kabylake Yoga uses 4W on video playback. I couldn't care about 0.15W unless I can get that from driver updates. It's a margin of error difference.
 
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TwistedAndy

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No, on Lunarlake it's on the compute tile. On Meteorlake it basically doesn't work. It is pretty looking at the die, but that's about it. It literally sits there pretty. Intel themselves said it saves a mere 150mW! My efficient Kabylake Yoga uses 4W on video playback. I couldn't care about 0.15W unless I can get that from driver updates. It's a margin of error difference.

Lunar Lake is similar to Meteor Lake (with the differences I described earlier), but with three tiles fused in one to save power.

Lion Cove cores in Arrow Lake can offer a higher IPC because of the bigger L2 cache and lower memory latency. But the difference is pretty small. I expect it to be nearly 5% with the fast memory.
 

TwistedAndy

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Why do you keep saying it's similar?
Lunar Lake has mostly the same structure, including NOC fiber, LP E-core island, separated GPU, IO controller, separated memory controller, etc. The most notable difference is the way the P-core cluster and the Side Cache are organized.

At the same time, the physical implementation is different. Three tiles in Meteor Lake become fused into one in Lunar Lake to save power, but this does not significantly affect performance.
 
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Hulk

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Regarding the 14% Lion Cove IPC increase despite the relatively massive architectural changes I'm wondering if either of the following could be a logical explanation?

1. It is possible we are starting to approach an IPC limit of some sort due to the maximum amount of parallelism that can be extracted from x86 code? What I'm asking here is if there is a point where no matter how much wider you make the design, and how much smarter the OoO engine becomes, there will still be unused structures due to the inherent serial nature of the code? If we look at IPC of x86 from its inception (IPC vs. time), would this plot be linear or exponential? I realize this depends very much on the software being used to gather the data.

2. If #2 is not the case (the sequential nature of the code isn't the main bottleneck) then could it be that the current P core architecture has maxed out from an IPC point-of-view and a completely new and different direction is required, something more along direction of Skymont?
 
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Henry swagger

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Regarding the 14% Lion Cove IPC increase despite the relatively massive architectural changes I'm wondering if either of the following could be a logical explanation?

1. It is possible we are starting to approach an IPC limit of some sort due to the maximum amount of parallelism that can be extracted from x86 code? What I'm asking here is if there is a point where no matter how much wider you make the design, and how much smarter the OoO engine becomes, there will still be unused structures due to the inherent serial nature of the code? If we look at IPC of x86 from its inception (IPC vs. time), would this plot be linear or exponential? I realize this depends very much on the software being used to gather the data.

2. If #2 is not the case (the sequential nature of the code isn't the main bottleneck) then could it be that the current P core architecture has maxed out from an IPC point-of-view and a completely new and different direction is required, something more along direction of Skymont?
Desktop lion cove will have higher ipc than lunar lake lion cove.. wait for intel to reveal it
 

ondma

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Regarding the 14% Lion Cove IPC increase despite the relatively massive architectural changes I'm wondering if either of the following could be a logical explanation?

1. It is possible we are starting to approach an IPC limit of some sort due to the maximum amount of parallelism that can be extracted from x86 code? What I'm asking here is if there is a point where no matter how much wider you make the design, and how much smarter the OoO engine becomes, there will still be unused structures due to the inherent serial nature of the code? If we look at IPC of x86 from its inception (IPC vs. time), would this plot be linear or exponential? I realize this depends very much on the software being used to gather the data.

2. If #2 is not the case (the sequential nature of the code isn't the main bottleneck) then could it be that the current P core architecture has maxed out from an IPC point-of-view and a completely new and different direction is required, something more along direction of Skymont?
What are the prospects for Nova Lake? Is it still a thing? I thought it (Nova Lake link) was supposed to be the biggest architectural change in Intel's history, and expected to bring a huge IPC gain (up to 50%)? Intel definitely needs to step up their game on the P core front.
 

SiliconFly

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There is no evidence that Arrow Lake is the same tile generation as MTL. I cannot be, different Node, different Fovo gen, different everything. I think they learned a lesson from MTL and implemented some changes to compensate the shortcomings.
Yep. We still don't know for sure. But initial rumors (even before MTL release) said ARL will reuse the same tile layout and the same soc tile with the 2LPE crestmont e cores will be reused. Yet to be confirmed.
 
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Doug S

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What are the prospects for Nova Lake? Is it still a thing? I thought it (Nova Lake link) was supposed to be the biggest architectural change in Intel's history, and expected to bring a huge IPC gain (up to 50%)? Intel definitely needs to step up their game on the P core front.

Nobody is making a 50% IPC gain in a single generation, that's simply not possible.

It also doesn't make sense they'd use TSMC N2 when 18A is supposed to be ready before it (if not 14A!) and they keep claiming they are going to achieve process leadership. That article reads like someone's wet dream about what they want to happen, much like how people here were building up all this hype for Zen 5 to gain 40% or more IPC.
 

Magio

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It also doesn't make sense they'd use TSMC N2 when 18A is supposed to be ready before it (if not 14A!) and they keep claiming they are going to achieve process leadership
I generally agree with what you said regarding the article being make-believe and 50% IPC a pipe dream, but just regarding this: Even if/when Intel regains process leadership (potentially with 18A) and even if/when that lead is significant (potentially with 14A or 10A), they will be continuing to leverage TSMC nodes long term.

Even if they could, which is not a certainty, ramp their leading edge nodes fast enough to cover their entire (high end) product line within reasonable time frames, they couldn't do that *and* have capacity to spare for foundry contracts with major players which are a key aspect of their new strategy.

So for the foreseeable future it will continue to make sense for Intel to have certain products, including halo products in certain segments, built on TSMC nodes partially or completely.
 

SiliconFly

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Nobody is making a 50% IPC gain in a single generation, that's simply not possible.

It also doesn't make sense they'd use TSMC N2 when 18A is supposed to be ready before it (if not 14A!) and they keep claiming they are going to achieve process leadership. That article reads like someone's wet dream about what they want to happen, much like how people here were building up all this hype for Zen 5 to gain 40% or more IPC.
If I remember right, very old rumors suggested that nova lake will offer 50% IPC uplift over GLC or something like that (not gen-over-gen). All these articles somehow manage to misinterpret one rumor and manage to spread more fake rumors based on the already unverified rumor and try to present it as facts. It's a systemic issue I'd say.
 

SiliconFly

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I generally agree with what you said regarding the article being make-believe and 50% IPC a pipe dream, but just regarding this: Even if/when Intel regains process leadership (potentially with 18A) and even if/when that lead is significant (potentially with 14A or 10A), they will be continuing to leverage TSMC nodes long term.

Even if they could, which is not a certainty, ramp their leading edge nodes fast enough to cover their entire (high end) product line within reasonable time frames, they couldn't do that *and* have capacity to spare for foundry contracts with major players which are a key aspect of their new strategy.

So for the foreseeable future it will continue to make sense for Intel to have certain products, including halo products in certain segments, built on TSMC nodes partially or completely.
Exactly! Intel's own leading edge nodes are gonna take a year or two to ramp up to full volume (and also improve yield). Until then they won't have the capacity they need and have to rely on external foundries to fulfill their own client/server orders that are on leading edge nodes.

"As you adequately put, the problem is capacity!". -The Architect. :)
 

Hulk

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I realize that Cinebench R23 ST isn't representative of a variety of software but I have this data that I believe is semi-reliable so I thought I would present this graph I created.

Intel was slowly "tick-tocking" along up until Skylake. The trouble with 10nm and a big rush to get Cypress Cove and Golden Cove out the door!

edit - Should be points/GHz, not MHz

1719789551740.png
 
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Doug S

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Exactly! Intel's own leading edge nodes are gonna take a year or two to ramp up to full volume (and also improve yield). Until then they won't have the capacity they need and have to rely on external foundries to fulfill their own client/server orders that are on leading edge nodes.

"As you adequately put, the problem is capacity!". -The Architect. :)

Its a really bad look if Intel's premium chips are coming out on someone else's process. They are supposedly looking at $15 billion in external foundry business by the end of the decade versus nearly $100 billion in internal volume, so it isn't as if they have a ton of external business pushing them to TSMC. They used to be able to supply their own needs - and they had a larger market share in those pre Zen days. So what happened? Do they have fewer fabs than they did 10 years ago?

I could see using TSMC for lower end/volume Celeron/Pentium/i3 type stuff, lower tier GPU chiplets, and the like but this is a rumor about some fabled new architecture that's going to let Intel from the wilderness and drive a stake in AMD's heart (or at least it would if that 50% was even close to real) Surely they could devote their best capacity to THAT, and use TSMC for all the trash that gets put into PCs costing $500 and under.
 

SiliconFly

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Its a really bad look if Intel's premium chips are coming out on someone else's process. They are supposedly looking at $15 billion in external foundry business by the end of the decade versus nearly $100 billion in internal volume, so it isn't as if they have a ton of external business pushing them to TSMC. They used to be able to supply their own needs - and they had a larger market share in those pre Zen days. So what happened? Do they have fewer fabs than they did 10 years ago?

I could see using TSMC for lower end/volume Celeron/Pentium/i3 type stuff, lower tier GPU chiplets, and the like but this is a rumor about some fabled new architecture that's going to let Intel from the wilderness and drive a stake in AMD's heart (or at least it would if that 50% was even close to real) Surely they could devote their best capacity to THAT, and use TSMC for all the trash that gets put into PCs costing $500 and under.
To be self-sustainable, Intel requires a lot of forward-looking vision. Something they seriously lacked until a few years ago. All thanks to the bean counters. For large capacity, new (heavy) investments in foundry is required and most importantly an investment now, takes a few years to translate to real world capacity.

That is exactly what has happened now. Intel is heavily invested in High-NA. In fact they've booked an entire years supply just to block the competition and build leading-edge capacity ahead of the rest. Assuming all goes well, Intel should have leading-edge capacity after the launch of 14A (not before and not during).

Until then, they have to rely a little bit on external foundries too for their leading-edge volume products (two years at least, even three maybe).
 

jpiniero

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Its a really bad look if Intel's premium chips are coming out on someone else's process. They are supposedly looking at $15 billion in external foundry business by the end of the decade versus nearly $100 billion in internal volume, so it isn't as if they have a ton of external business pushing them to TSMC. They used to be able to supply their own needs - and they had a larger market share in those pre Zen days. So what happened? Do they have fewer fabs than they did 10 years ago?

Um... this has been discussed just in this thread multiple times. Intel doesn't have the money.