Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 385 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Tigerick

Senior member
Apr 1, 2022
696
602
106
PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



Clockspeed.png
 

Attachments

  • PantherLake.png
    PantherLake.png
    283.5 KB · Views: 24,006
  • LNL.png
    LNL.png
    881.8 KB · Views: 25,490
Last edited:

AcrosTinus

Member
Jun 23, 2024
113
101
76
Rental Units would be '"cool". ARL 8+32 would be interesting. Beast Lake 16+32 would be a killer. Royal Core might be cool. Will we ever see any of them? Seems like every time Intel supposedly has something "cool" in the pipeline it either is late, gets cancelled, or simply does not live up to the hype. Point being? Just because Lion Cove is potentially a flexible architecture, considering the way Intel has executed lately, I certainly don't expect them to pull some magic out of the hat and give LC in ARL more than a token increase in IPC compared to the same core in LL. At best perhaps they will be able to make some modifications to Lion Cove in RL-R to make it more performant.
This smug MLID way of dismissing a company based on not realized hype and rumors is not fair. A heavy research and development company like Intel will have successful stuff in the lab and stuff that is nice but not economical. (Rest in peace 3DXPoint, you somehow made it through the beancounters but too soon to be appreciated)

The Advancement Intel made on Lion Cove allows them to easier iterate and customize for a particular use case, this is another de-risking strategy from Pat. The nodes don't lock anymore due to standardized tools and possible TSMC outsourcing.

Fingers crossed for a 10+% increase in ST performance each year which would mean 30% or more in a 3Y upgrade cycle, this is great.
 

SiliconFly

Golden Member
Mar 10, 2023
1,541
897
96
...dismissing a company...
Totally agree. I wouldn't casually dismiss them anymore. A few years back, during most Intel announcements, we were pretty much certain that Intel would disappoint us somehow. And of course, they did it most of the time (either late or behind competition or both). How they were gonna disappoint us was the big surprise. :)

But that doesn't apply anymore. The new Intel is far better than the old one. Better execution. Better tech. Better vision. Even the products are able to stand up to competition! Thats not trivial.

Fingers crossed...
Me too. Hoping they come out with something good this time for the desktop.
 

majord

Senior member
Jul 26, 2015
493
641
136
There has been discussion already stating that Lion Cove is not a single architecture, but an umbrella term for a group of designs based on a larger blueprint. Remember "Sea of Fubs to a Sea of Cells".

The P core team in their video clearly said that they've moved not only to industry standard design tools, but now the design is also process agnostic and also now they can rapidly slice and dice the design as they wish.

Everyone does this already.. If there was some solid info that the version of Lion cove in Lunar Lake was some sort of cut down variant of a larger core , then maybe it would be worth speculating. Assuming they can just throw things arbitrarily at the core to pull meaningful IPC [general] gains is a bit 'pie in the sky'.
 

CouncilorIrissa

Senior member
Jul 28, 2023
540
2,120
96
There has been discussion already stating that Lion Cove is not a single architecture, but an umbrella term for a group of designs based on a larger blueprint. Remember "Sea of Fubs to a Sea of Cells".

The P core team in their video clearly said that they've moved not only to industry standard design tools, but now the design is also process agnostic and also now they can rapidly slice and dice the design as they wish.

With so much of power and flexibility at their disposal, I don't think they're gonna just release the same LNC yet again with ARL (defeats the entire purpose). And it also aligns well with the initial rumors as well.

You can always claim they didn't explicitly state ARL's LNC will be different from LNL's LNC. But at the same time, I can also claim that they didn't explicitly state ARL's LNC will be the same as LNL's LNC. The jury is still out on that one.

And looking at all the published info, I believe ARL's LNC is gonna be more different than some assume it to be. 20% IPC uplift over RWC is entirely possible. Maybe more if they've done something cool.
I think there's little reason to have two significantly different core designs on client.
I personally think it's server where LNC will be at its most different compared to LNL, rather than ARL, much like Skylake-SP had a different L2 and support for AVX-512 that was missing from Skylake-S.
 

Hulk

Diamond Member
Oct 9, 1999
4,525
2,515
136
I think there's little reason to have two significantly different core designs on client.
I personally think it's server where LNC will be at its most different compared to LNL, rather than ARL, much like Skylake-SP had a different L2 and support for AVX-512 that was missing from Skylake-S.
Maybe with the addition of HT for server as well.
 

Hulk

Diamond Member
Oct 9, 1999
4,525
2,515
136
Lunar Lake is going to be a big improvement for small form factor laptops. Imagine a low power laptop with 8 Raptor Cove cores. Pretty good. Now imagine 4 Lion Cove + 4 Raptor Cove. Even better. Top of the stack parts might well compete with the 14500.
 

ondma

Diamond Member
Mar 18, 2018
3,005
1,528
136
Possibly a bit more than that.


I'm guessing Lion Cove in ARL-R. It's always a possibility. But it's a bit too far.
I meant ARL-R for improved Lion Cove of course (too many lakes). I too had thought that Intel was back on track and executing well. However, the somewhat disappointing Meteor Lake release, the fact that they had to do a Raptor lake refresh instead of having a new architecture, and the stability problems with 13th and 14th gen (and the lack of a quick fix) are putting a lot of doubt back in my mind.
 

TwistedAndy

Member
May 23, 2024
159
150
76
LNC in LNL benefits from an on-die memory controller. MTL has the memory controller on the SoC. How's Arrow Lake going to fare in this regard, is the overall structural layout the same as MTL, with the mem controller still situated on the other tile?

Lunar Lake is similar to Meteor Lake in this regard. Intel removed the memory controller from the P-core ring to have an option to shut down the whole P-core cluster.

Arrow Lake will have the memory controller on the ring as we have on Alder Lake and Raptor Lake. If we compare Lion Cove in Lunar Lake and Arrow Lake, there will be ~ a 5% difference in terms of IPC, mostly because of larger caches and faster memory with lower latencies.

I personally think it's server where LNC will be at its most different compared to LNL, rather than ARL, much like Skylake-SP had a different L2 and support for AVX-512 that was missing from Skylake-S.

Yep. One of the reasons why Intel has switched to a new design approach is to be able to easily toggle some features on the hardware level. There is no sense in spending the die space and power budget on the AVX-512 support on hybrid platforms. Another toggle is the HT support.

Both AVX-512 and HT will be available for workstation and server SKUs.
 

TwistedAndy

Member
May 23, 2024
159
150
76
So the mem controller is moved to the compute tile? Because AFAIK MTL not only has the mem controller off the ring, it's on the SoC tile too.

Lunar Lake and Meteor Lake share the same concept: the P-cores (a CPU cluster) and the GPU can be dynamically turned off to save power. That's why Intel moved the memory controller, LP E-cores, media engine, and other stuff to the SoC tile/cluster, which is always active.

There's no big difference in how those structures are implemented: as a separate tile (Meteor Lake) or an independent cluster (Lunar Lake).

In Meteor Lake Intel has introduced the NOC fabric to connect all the blocks:

download.jpg

In Lunar Lake, the structure will be very similar, but in addition to the memory controller, we will have the Side Cache (SLC). It will probably be something like a buffer for a memory controller. That will explain why they are placed closely on the actual chip.

From my perspective, in Arrow Lake, it makes sense to use the memory controller on the ring because there is no urgent need to turn off the P-core cluster or a GPU complex.

But Intel may want to use the NOC fabric on Arrow Lake as well. In this case, we can have LP E-cores, Side Cache, and other stuff on Arrow Lake.

We'll get more details on Intel's decision in August.
 
Last edited:
  • Like
Reactions: carancho

DavidC1

Senior member
Dec 29, 2023
939
1,470
96
Mind you folks, that Computex crashed the "IPC" dreams of both Intel and AMD folks.

Memory bandwidth is a situational improvement when it comes to general purpose compute. Memory latency on the other hand is different, but it also needs to be significant improvement.

There seems to be a minor Zen 5-level hype people are trying to build up with Arrowlake's Lion Cove. There's nothing that suggests the improvement will be anywhere significant. Especially when Arrowlake inherits the Meteorlake's configuration.

I am expecting 2-3% best-case-scenario for Arrowlake, and for average, essentially zero.

@TwistedAndy There's little in common between LNL and MTL except both are using "Tiles" and both are made by Intel. Arrowlake INHERITS Meteorlake's configuration.

Some things in Arrowlake are a straight up downgrade such as the ACM+ based graphics tile.
I meant ARL-R for improved Lion Cove of course (too many lakes). I too had thought that Intel was back on track and executing well. However, the somewhat disappointing Meteor Lake release, the fact that they had to do a Raptor lake refresh instead of having a new architecture, and the stability problems with 13th and 14th gen (and the lack of a quick fix) are putting a lot of doubt back in my mind.
Keep in reminder that development cycles can take 3-4 years, often more. Meteorlake is the effect of BK's management starting in 2014.

It is much easier to break something than to repair it or make it. At some point in development the only thing even a stellar management can manage to do is stop the delays from getting worse.

Sierra Forest, Lunar Lake, and other products coming out NOW will determine the strength of Gelsinger's management. The more time passes, more will fall on him, good or bad.
 

TwistedAndy

Member
May 23, 2024
159
150
76
@TwistedAndy There's little in common between LNL and MTL except both are using "Tiles" and both are made by Intel. Arrowlake INHERITS Meteorlake's configuration.

Here's the Lunar Lake layout:

1719743442826.png

We have mostly the same configuration as Meteor Lake with the NOC fabric joining LP E-cores cluster, P-cores cluster, NPU, Media, GPU, IO-tile (at the bottom), and Side Cache as a buffer for the memory controller.

The main difference is the organization of P-cores (MTL has a P- and E-core CPU cluster), the number of E-cores, and the Side Cache, which buffers the memory.

But yes, In Arrow Lake, we will have a CPU cluster similar to Meteor Lake and, probably, with a similar NOC fabric and Side Cache.
 

coercitiv

Diamond Member
Jan 24, 2014
6,677
14,272
136
We have mostly the same configuration as Meteor Lake with the NOC fabric joining LP E-cores cluster, P-cores cluster, NPU, Media, GPU, IO-tile (at the bottom), and Side Cache as a buffer for the memory controller.
AFAIK in MTL the CPU cores are connected via a ring bus, with the SoC tile having a ring stop to collect traffic that is then passed to the SoC NOC fabric. If this is true, then calling it "mostly the same configuration" is a bit forced.

soc-11.jpg

mtl-ring.png

Granted the part about he SoC ring stop is based on some assumptions by Chips and Cheese, if there's more up-to-date info on the subject it would be great if folks could share a link.
 

Hulk

Diamond Member
Oct 9, 1999
4,525
2,515
136
The issue I'm trying to wrap my head around with increased memory performance from Lunar Lake to ARL is that it seems people are comparing the memory structure of MTL to LNL. They are quite different with LNL being much faster and this will make Lion Cove IPC increase from LNL to ARL difficult.

For one thing, LNL uses 16GB or 32GB on package LPDDR5x-8533 DRAM (Low Power) memory with up to 8.5GT/sec per chip. I don't know about latency but that's pretty good for mobile main memory access. The fact that it is on package bodes well for latency I would think, not to mention the fact that Intel can tighten up the guard band for timings since they are controlling all settings for memory. ie they don't have to allow for lowest common denominator.

The other thing is the additional cache level for the Lion Cove cores, which will help mitigate memory subsystem performance loss in mobile as compared to desktop.

Intel really seems to have "thought out" LNL, perhaps they did with ARL as well and I'll be surprised, but I'm thinking maybe 3% better IPC for ARL P cores over LNL.
 
  • Like
Reactions: carancho

DavidC1

Senior member
Dec 29, 2023
939
1,470
96
We have mostly the same configuration as Meteor Lake with the NOC fabric joining LP E-cores cluster, P-cores cluster, NPU, Media, GPU, IO-tile (at the bottom), and Side Cache as a buffer for the memory controller.
The difference might seem subtle, but it's big.

(continued...)
AFAIK in MTL the CPU cores are connected via a ring bus, with the SoC tile having a ring stop to collect traffic that is then passed to the SoC NOC fabric. If this is true, then calling it "mostly the same configuration" is a bit forced.
The thing about buses is that if ANY core needs access, then it needs to be on. Therefore, Lunarlake SEPARATES the E core bus from the P core, so it can be throttled independently.

Compared to on-die, even Foveros Omni is a negative with increased power and latency requirements. Direct is worse, and vanilla Foveros even more so. They need to mitigate Foveros loss FIRST, which LNL has an advantage over ARL because it has less tiles.
For one thing, LNL uses 16GB or 32GB on package LPDDR5x-8533 DRAM (Low Power) memory with up to 8.5GT/sec per chip. I don't know about latency but that's pretty good for mobile main memory access. The fact that it is on package bodes well for latency I would think, not to mention the fact that Intel can tighten up the guard band for timings since they are controlling all settings for memory. ie they don't have to allow for lowest common denominator.
They could, but since they only talked about PHY power reduction, it's safe to assume that's the focus for Lunarlake.

Bandwidth only benefits a subsection of workloads after a certain point. It is latency where it benefits general purpose compute. I doubt latency improved on LNL.

It's the classic car example. Increasing max speed benefits EVERYONE. Increasing lanes or number of cars owned does not always benefit YOU the individual.
The other thing is the additional cache level for the Lion Cove cores, which will help mitigate memory subsystem performance loss in mobile as compared to desktop.
This is a good point too. Oftentimes the effort taken to improve performance by a few % or just to mitigate losses are a bigger deal for low end parts.

Prescott didn't improve, but the Celeron Prescott improved greatly. Unlike on the high end, Celeron based on the Prescott was more than 20% better per clock compared to Celeron based on Northwood. Northwood was ok, Celeron sucked. On Prescott, it reversed it.
Intel really seems to have "thought out" LNL, perhaps they did with ARL as well and I'll be surprised, but I'm thinking maybe 3% better IPC for ARL P cores over LNL.
I can believe this, but no more. Remember the "big jump" only brought us 14%. And Lunarlake has the advantage of only needing two tiles versus Arrowlake's three.

Look how much better Emerald Rapids is by moving to a two-tile setup for compute. Memory subsystem performance improved substantially. It is not so much bandwidth but latency that improved.
 
  • Like
Reactions: Hulk

TwistedAndy

Member
May 23, 2024
159
150
76
Maybe worth a mention. Lunar Lake has a more advances NoC fabric than MTL. ARL should inherit the newer one. Not much details yet, but should improve interconnect bandwidth & latency.

Maybe there will be some adjustments, but I don't think they will be so noticeable.

AFAIK in MTL the CPU cores are connected via a ring bus, with the SoC tile having a ring stop to collect traffic that is then passed to the SoC NOC fabric. If this is true, then calling it "mostly the same configuration" is a bit forced.

Yes, correct. The P- and regular E-cores in MTL are connected using a ring bus, which has one connection to NOC (compute tile NOC agent). The same approach will probably be used in Arrow Lake.

In Lunar Lake, there's an LLC connecting P-cores and the NOC agent to connect to the NOC fabric:

LUNAR-LAKE-0160.jpg

On this slide, Intel labeled NOC as "North Fabric".

So, in terms of internal organization, Arrow Lake is expected to be closer to Meteor Lake than to Lunar Lake, but the difference is mostly in the connection to NOC.

Also, it's probable that for ARL-S and HX Intel will decide to use the old approach with one ring for all the cores, GPU, memory controller, etc.

Intel really seems to have "thought out" LNL, perhaps they did with ARL as well and I'll be surprised, but I'm thinking maybe 3% better IPC for ARL P cores over LNL.

Yes, the IPC difference between ARL and LNL is expected to be pretty small (~5%). LPDDR memory, in general, has higher latencies.
 

DavidC1

Senior member
Dec 29, 2023
939
1,470
96
@TwistedAndy How can you claim they are the same, when they are clearly more different the more you look at them?

-P cores and E cores are entirely separate on LNL, not on ARL. The NOC will have to be low bandwidth to save power. The important stuff like the P/GPU/NPU is on the same ringbus anyway.
-SLC cache for power saving on LNL. Where would Intel put the 8MB system cache? It is not a significant amount by any means to benefit a 8+16 CPU for L4. Lunarlake has 10MB L2 caches for the 4 cores, already eclipsing the size of the SLC. For ARL it has to be significant because assuming 4MB per E core clusters and 3MB L3 per P cores it will have 40MB L3,so we're talking 64MB+, preferably 128MB minimum for the L4 to be of any benefit. In fact, we should not expect SLC for Arrowlake.
-Two tiles versus four. CPU, GPU, SoC, and IO for ARL versus Compute + Platform for LNL. Much saner approach needing much less connections and lower latency and faster communication for lower power.
-Same die memory controller for LNL. So in essence, Lunarlake is a natural progression of the on package CPU+PCH setup that -U chips used forever but with a more advanced Foveros interconnect versus MTL doing YOU GET A TILE! YOU GET A TILE! YOU ALSO GET A TILE!!*

*References to Oprah totally intentional.
 

DavidC1

Senior member
Dec 29, 2023
939
1,470
96
My guess is if Lunarlake is more popular than Intel expects, then they'll make a derivative of Pantherlake to be a direct successor.*

Because Pantherlake is using the P+E+LPE setup again. It is possible that we need THIRD wildly different SoC. One for server, one for desktops and high performance laptops and one for ultra low power laptops.

*Lunarlake might be a one off thing just to fend off ARM. If they stop the momentum, it'll take time for them to lick their wounds and come back again. Then Intel can go back to the less optimal but cheaper MTL/PTL derivatives.

If that's the case I hope Gelsinger is the CEO that breaks this mentality and realize that they should do it first. Andy Grove's "Only the paranoid" survive.

If Intel had low power Atom cores without being forced by ARM, then they wouldn't have had to worry about competition. This company has been always reactionary, never a true leader.
 

TwistedAndy

Member
May 23, 2024
159
150
76
How can you claim they are the same, when they are clearly more different the more you look at them?

I claimed the structure is similar, not the same. In the previous messages, I described the differences ;)

-SLC cache for power saving on LNL. Where would Intel put the 8MB system cache? It is not a significant amount by any means to benefit a 8+16 CPU for L4. Lunarlake has 10MB L2 caches for the 4 cores, already eclipsing the size of the SLC. For ARL it has to be significant because assuming 4MB per E core clusters and 3MB L3 per P cores it will have 40MB L3,so we're talking 64MB+, preferably 128MB minimum for the L4 to be of any benefit.

SLC cache is required to alleviate the missing L3 cache for LP E-cores in the first place.

I'm not entirely sure which approach Intel will decide to use for Arrow Lake: the old one without NOC and the memory controller on the ring or the newer one with NOC and a separate memory controller. Technically, the new approach with NOC is more flexible, but the additional NOC latency costs 1-3% IPC (Meteor Lake vs Raptor Lake).
 

AcrosTinus

Member
Jun 23, 2024
113
101
76
It think it will, everyone seems to agree that the tile generation of Arrow Lake will still be similar to Meteor Lake without evidence.
If Intel wants this to be a low latency gaming and productivity SKU, there might be some changes to the active substrate, fevoros and packaging, it is not the same.

Hence, I believe the MEM controller is on the ring or they found a way to compensate the latency.
 

DavidC1

Senior member
Dec 29, 2023
939
1,470
96
SLC cache is required to alleviate the missing L3 cache for LP E-cores in the first place.

I'm not entirely sure which approach Intel will decide to use for Arrow Lake: the old one without NOC and the memory controller on the ring or the newer one with NOC and a separate memory controller. Technically, the new approach with NOC is more flexible, but the additional NOC latency costs 1-3% IPC (Meteor Lake vs Raptor Lake).
SLC is the same approach for Apple parts, to lower power. Their problem was their IO(the chipset) had higher power. By having trivial uncore/IO data(compared to compute requirements) in SRAM, it saves an enormous amount of power. Power savings first, then performance.

I am not sure why you think Arrowlake will use a different approach when it's basically Meteorlake with different tiles. GPU being based on ACM is a proof of that. So you are saying that ARL will have a IMC on compute tile AND disabled one on the SoC Tile?
Hence, I believe the MEM controller is on the ring or they found a way to compensate the latency.
Cause Intel always made decisions that made sense right? And they never stumbled?:rolleyes:
 

AcrosTinus

Member
Jun 23, 2024
113
101
76
The difference might seem subtle, but it's big.

(continued...)

The thing about buses is that if ANY core needs access, then it needs to be on. Therefore, Lunarlake SEPARATES the E core bus from the P core, so it can be throttled independently.

Compared to on-die, even Foveros Omni is a negative with increased power and latency requirements. Direct is worse, and vanilla Foveros even more so. They need to mitigate Foveros loss FIRST, which LNL has an advantage over ARL because it has less tiles.

They could, but since they only talked about PHY power reduction, it's safe to assume that's the focus for Lunarlake.

Bandwidth only benefits a subsection of workloads after a certain point. It is latency where it benefits general purpose compute. I doubt latency improved on LNL.

It's the classic car example. Increasing max speed benefits EVERYONE. Increasing lanes or number of cars owned does not always benefit YOU the individual.

This is a good point too. Oftentimes the effort taken to improve performance by a few % or just to mitigate losses are a bigger deal for low end parts.

Prescott didn't improve, but the Celeron Prescott improved greatly. Unlike on the high end, Celeron based on the Prescott was more than 20% better per clock compared to Celeron based on Northwood. Northwood was ok, Celeron sucked. On Prescott, it reversed it.

I can believe this, but no more. Remember the "big jump" only brought us 14%. And Lunarlake has the advantage of only needing two tiles versus Arrowlake's three.

Look how much better Emerald Rapids is by moving to a two-tile setup for compute. Memory subsystem performance improved substantially. It is not so much bandwidth but latency that improved.
There is no evidence that Arrow Lake is the same tile generation as MTL. I cannot be, different Node, different Fovo gen, different everything. I think they learned a lesson from MTL and implemented some changes to compensate the shortcomings.