Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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Hulk

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You get it, I think Pat knows what is he is doing, everything is about de-risking and building resilience while pushing forward so that the past cannot repeat itself. Proof is the "I bet the company on 18A" in reality there is 20A that generates insight and corrections for 18A before it goes into volume. Again, I might be a bit too hopeful due to buying the intel dip but everything is alright as of now.
When I first heard Intel would be using TSMC my first reaction was, "Intel has surrendered the foundry business." But now I'm understanding "the right node for the right transistors" makes sense. Intel can't do it all and they can maximize their foundry by picking and choosing where to produce the various tiles and on what processes.

Would I be correct in assuming Intel does have an advantage by still having a foundry business or is it a total liability? I'm thinking that at the end of the day the cheaper you can produce your parts the better. Raptor Lake is pretty huge but they could "swallow" that cost because they are the foundry.
 

poke01

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Mar 8, 2022
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I’m keeping expectations low about performance but at least one thing is confirmed and that efficiency is confirmed to have improved due to the TSMC node.

We can discussions about who is better when both release, each week the pendulum swings either way.

I don’t people understand what type of node Intel is coming off from. Intel 7 to TSMC N3B is like going from on iPhone 7 to iPhone 15 Pro or an S6 to S23 Ultra.
 

Doug S

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When I first heard Intel would be using TSMC my first reaction was, "Intel has surrendered the foundry business." But now I'm understanding "the right node for the right transistors" makes sense. Intel can't do it all and they can maximize their foundry by picking and choosing where to produce the various tiles and on what processes.

Would I be correct in assuming Intel does have an advantage by still having a foundry business or is it a total liability? I'm thinking that at the end of the day the cheaper you can produce your parts the better. Raptor Lake is pretty huge but they could "swallow" that cost because they are the foundry.


I think Intel would very much prefer to stop using outside foundries, at least for any process that was current in the past decade. They have no choice today because they don't have enough capacity to serve their own needs, let alone that of outside customers they're trying to take on. That will be true for most of the current decade.

I don't buy the argument that it is more profitable to make chips in house. Sure, they double dip on profit - making money both on producing the chip (what TSMC is making from AMD) and on selling the chip (what AMD is making from the markup they charge on the chips TSMC made for them) but if more total dollars of profit was the goal they should be like Samsung and make smartphones, ships, NAND, TVs, and everything in between. Having the foundry in house was an advantage for Intel in some ways (like designing the process towards the chips they wanted to make) but was a disadvantage in ways too - dysfunction like your example where they could think "well this chip is pretty large and has bad yields as a result but that's fine because we have spare capacity in our fabs that would otherwise be wasted"

Given that AMD and TSMC are both profitable, there are clearly profits to be had in both businesses. But they are so different in terms of capital requirements, business cycles, etc. that I don't believe it makes sense for both to be under one roof. When you add in the fact Intel's chip division competes in some way with many of the biggest potential customers like Apple, Nvidia, Qualcomm and AMD, it is clear they need to spin off the foundry once it is able to stand on its own. I would say they reach that point when they do more business in wafer volume and revenue with outside customers than they do internally. If they are successful and aggressive enough in fab buildout they should be able to reach that position in the early 2030s, though they'd see the runway towards that several years earlier - so 2028/2029 is the earliest I'd expect to see such an announcement.
 

AcrosTinus

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I think Intel would very much prefer to stop using outside foundries, at least for any process that was current in the past decade. They have no choice today because they don't have enough capacity to serve their own needs, let alone that of outside customers they're trying to take on. That will be true for most of the current decade.

I don't buy the argument that it is more profitable to make chips in house. Sure, they double dip on profit - making money both on producing the chip (what TSMC is making from AMD) and on selling the chip (what AMD is making from the markup they charge on the chips TSMC made for them) but if more total dollars of profit was the goal they should be like Samsung and make smartphones, ships, NAND, TVs, and everything in between. Having the foundry in house was an advantage for Intel in some ways (like designing the process towards the chips they wanted to make) but was a disadvantage in ways too - dysfunction like your example where they could think "well this chip is pretty large and has bad yields as a result but that's fine because we have spare capacity in our fabs that would otherwise be wasted"

Given that AMD and TSMC are both profitable, there are clearly profits to be had in both businesses. But they are so different in terms of capital requirements, business cycles, etc. that I don't believe it makes sense for both to be under one roof. When you add in the fact Intel's chip division competes in some way with many of the biggest potential customers like Apple, Nvidia, Qualcomm and AMD, it is clear they need to spin off the foundry once it is able to stand on its own. I would say they reach that point when they do more business in wafer volume and revenue with outside customers than they do internally. If they are successful and aggressive enough in fab buildout they should be able to reach that position in the early 2030s, though they'd see the runway towards that several years earlier - so 2028/2029 is the earliest I'd expect to see such an announcement.
I don't want to get political but for the west the foundry is a burden worth carrying. That is the main reason I invested into Intel.
 

Doug S

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I don't want to get political but for the west the foundry is a burden worth carrying. That is the main reason I invested into Intel.

Intel doesn't need to own the foundry under the same roof as their chip business for that though. If they spun it off under a separate stock symbol and management what you say is still true.
 

inquiss

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Oct 13, 2010
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Neither. After years of lagging competition, Intel has finally caught up (in almost all areas). That in itself is a massive feat! They're both almost at par now. A few percent points difference shouldn't be considered a big win.

Things may actually change a lot depending on how both the companies execute in the future. But not anytime now imho.

Based on LNC/Zen5 leaks, it looks like 2024 is gonna be the year of the equals.
Doubt it. Lunar is good, sure, but its not competing in the same race. Lunar lake will dominate the small core count stuff, and tablets, strix anything higher. So like, not equals?
 

SiliconFly

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... Lunar lake will dominate the small core count stuff...
Very much possible. But how big is the ULP market? Not sure. But don't think it's big enough to make a huge difference.

...for the west the foundry is a burden worth carrying. ...
Surely. For the west it's worth it. Not for Intel. It's dragging the other units down.

Intel doesn't need to own the foundry under the same roof as their chip...
Very true. But it does have its own advantages though.
 
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SiliconFly

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I’m keeping expectations low about performance but at least one thing is confirmed and that efficiency is confirmed to have improved due to the TSMC node.

We can discussions about who is better when both release, each week the pendulum swings either way.

I don’t people understand what type of node Intel is coming off from. Intel 7 to TSMC N3B is like going from on iPhone 7 to iPhone 15 Pro or an S6 to S23 Ultra.
Totally agree. The massive node jump is gonna contribute a lot to increased efficiency mostly. But this increase is only sufficient enough to catch up to competition as of now (or maybe exceed a bit at best). For all practical purposes, we can safely assume they're mostly at par this year.

Well if Intel has caught up on node shoulder they be superior to AMD.

Afterall intel on a node behind was equal or a little better than Zen 4 in IPC. Though power usage much higher and stability issues 13th and 14th Gen kind of negated that.

But if Intel is better on node shouldn't they be better and superior given they were equal on inferior node despite power and stability issues om the 10nm inferior node.
Not really. For example, Intel is still stuck with their power hungry P core in servers (it's still using RWC). Nothing much to expect there. In clients, the LNC leaks didn't indicate much (but an official ARL's LNC reveal might say something entirely different; who knows).

At this point, Intel needs to go the extra mile with its P core architecture to be "superior to AMD". No sure whether ARL's LNC can pull it off. I'll be interesting if it happens. But it's a definite possibility with future P core architectures.
 

dttprofessor

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Maybe Intel 3 can tame the beast. From the benchmarks I saw and the ones I ran myself, Zen 4 is an inferior core but more balanced than GLC, RWC, RPC. The SPEC results show a slight advantage for Intel and a huge one if you artificially manage to load up the backend to the max.
I don't know for sure but Intel's mesh and old node resulted in higher power draw and lower clocks. AMD could use the bleeding edge on a less wide core, using less power on a better communication protocol(infinity fabric?) that scales better, meaning higher clocks on server.

After Intel fixes their nodes, Intel 3 is promising, their mesh interconnect might need a second look. (not a hardware designer, the mesh might be just the right thing)
It's balance,CLF is 24 cores per tile *12.
Of course CLF is E core.
 

naukkis

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While I generally agree with your take on flagship vs. flagship MT performance, when it comes to i7 and especially the the i5, Intel will have the better offering. The only problem is RPL already has the better i5 over Zen 4 and that does not stop AMD from selling the R5 in particular. The halo effect from the flagships gaming CPU and the somewhat bad rep of the E cores (as in not great for games) make people chose the 6P product from AMD even when Intel has a better all-rounder in the form of 13500 for example.


According to Intel the HT performance gains is 1.3x, that's pretty close to the 0.75 factor used by @ondma in his napkin math.

See 30% uplift for 120% power. At other slide they tell that by dropping HT they could increase power efficiency 15%. So it's a wash - there's no benefit from HT on current power limited cpus. Specially hybrid cpu's will gain performance by giving more power to more efficient E-cores in MT workloads. And that's just what Intel did show in those slides you are referring.
 

coercitiv

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At other slide they tell that by dropping HT they could increase power efficiency 15%.
Conveniently forgetting their third slide showing the HT enabled core having 5% better power efficiency than even the optimized core. Intel made the slides to explain why removing HT was a good idea in a product aimed at lightly threaded workloads and low energy consumption. If they removed HT from ARL then I hope they used the optimized LNC core layout, and not just disable SMT at firmware level, otherwise this will truly be a loss-loss scenario. (at least according to your PoV)

Meanwhile, as more voices pile in to explain why ARL has the winning cards on all fronts - better P core optimization by removing SMT, better E core thanks to the excellent Skymont results, more cores in general and better node thanks to the denser and slightly more power efficient N3B - it would be quite awkward if desktop Zen 5 manages to stay close or even match it in MT performance. With ARL holding all the aces, it shouldn't even get close.
 

SiliconFly

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Conveniently forgetting their third slide showing the HT enabled core having 5% better power efficiency than even the optimized core. Intel made the slides to explain why removing HT was a good idea in a product aimed at lightly threaded workloads and low energy consumption. If they removed HT from ARL then I hope they used the optimized LNC core layout, and not just disable SMT at firmware level, otherwise this will truly be a loss-loss scenario. (at least according to your PoV)

Meanwhile, as more voices pile in to explain why ARL has the winning cards on all fronts - better P core optimization by removing SMT, better E core thanks to the excellent Skymont results, more cores in general and better node thanks to the denser and slightly more power efficient N3B - it would be quite awkward if desktop Zen 5 manages to stay close or even match it in MT performance.
Just saw a Zen5 Strix APU GB6 ST leak in X. And it's close to expectations. This year the competition is gonna be tough on both fronts (ST & MT). Exciting times ahead...

With ARL holding all the aces, it shouldn't even get close.
Too soon to be so sure! Zen is also known for coming up with surprises.
 

naukkis

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Conveniently forgetting their third slide showing the HT enabled core having 5% better power efficiency than even the optimized core.
Take a closer look. Optimized 1t-core have that 5% better power-efficiency even against total throughput of 2-threads of HT-core. Only thing SMT core does better is performance per area - and that's forgivable for better performance.

Math could be difficult - but 15% perf increase at isopower is massive. It's more than 30% increase at 120% power level if power is limited. And it is, those stupid unlimited power levels Intel did with previous generations backfired and we will not see them in the future - and in hindsight should not have seen at all.
 
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lightisgood

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Abwx

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Math could be difficult - but 15% perf increase at isopower is massive. It's more than 30% increase at 120% power level if power is limited. And it is, those stupid unlimited power levels Intel did with previous generations backfired and we will not see them in the future - and in hindsight should not have seen at all.
Why should a core with SMT be compared to a SMT less core at different throughputs.?.
This obviously skew the results since that s not an apple/apple comparison, what matter is what power is to be used at a given and same throughput.

At 30% better throughput with SMT you can downclock by 1.30x and hence get the same throughput at about 1.2 x 0.56 = 0.67x the power, wich is 50% better perf/watt at isothroughput.

I also read that you said that the power saved by removing SMT can be transfered to the e cores, but this amount to clock them higher, wich will increase even more the inefficency of the SMT less non solution.
 

Geddagod

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Meanwhile, as more voices pile in to explain why ARL has the winning cards on all fronts - better P core optimization by removing SMT, better E core thanks to the excellent Skymont results, more cores in general and better node thanks to the denser and slightly more power efficient N3B - it would be quite awkward if desktop Zen 5 manages to stay close or even match it in MT performance. With ARL holding all the aces, it shouldn't even get close.
Reminds me of a certain P core on Intel 7 ultra outright beating another certain P core on TSMC N5. Wasn't that awkward then....
Take a closer look. Optimized 1t-core have that 5% better power-effciency even against total throughput of 2-threads of HT-core. Only thing SMT core does better is performance per area - and that's forgivable for better performance.
I'm pretty sure Intel has stated that SMT also gives a core better perf/watt.
CU9 288V has slightly +0.1GHz clock boost, too (c.f. CU9 185H).
It looks like that N3B is almost same Intel 4 on peak FinFET performance.
I think there are 5GHz barriers.

Now I'm excited about Intel 3's peak FinFET performance.
Doubt it. Just saying, 15-30 watt Zen 4 mobile CPUs also only clocked up to 5.1GHz, despite, as we know, Zen 4 is able to hit what, 5.7, 5.8GHz?
 

naukkis

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Why should a core with SMT be compared to a SMT less core at different throughputs.?.
This obviously skew the results since that s not an apple/apple comparison, what matter is what power is to be used at a given and same throughput.

At 30% better throughput with SMT you can downclock by 1.30x and hence get the same throughput at about 1.2 x 0.56 = 0.67x the power, wich is 50% better perf/watt at isothroughput.

I also read that you said that the power saved by removing SMT can be transfered to the e cores, but this amount to clock them higher, wich will increase even more the inefficency of the SMT less non solution.

Intel p-core team did in their slides. Their optimized SMTless core beat SMT-version throughput even when counting SMT-version two threads together. Your calculations aren't right because you are comparing against cpu with HT running one thread instead of SMT less optimized core like Intel did.

And if e-cores would need to clock above their efficiency point Intel could increase those count - ruining big cores with SMT isn't bringing any benefits to hybrid cpus. That's too is well mentioned in Intel P-core team presentation.
 
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Abwx

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Intel did in their slides. Their optimized SMTless core beat SMT-version throughput even when counting SMT-version two threads together. Your calculations aren't right because you are comparing against cpu with HT running one thread not to SMT less optimized core like Intel did.

My calculations are right, it s just that Intel is aware that not everybody can do efficency evaluations.

And actually what they are doing is to increase the core count as a mean to increase efficency by using 2 cores instead of one, that s the only case where their discourse hold.

Rather than using a core that output 130 with SMT at a frequency of 100 and power of say 13W they use 2 comparable cores that are clocked at 65 to get a 130 throghput, in this case their 2 cores will consume 8W for the same 130 throughput, wich is 62.5% better perf/Watt.
 
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naukkis

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My calculations are right, it s just that Intel is aware that not everybody can do efficency evaluations.

And actually what they are doing is to increase the core count as a mean to increase efficency by using 2 cores instead of one, that s the only case where their discourse hold.

Rather than using a core that output 130 with SMT at a frequency of 100 and power of say 13W they use 2 comparable cores that are clocked at 65 to get a 130 throghput, in this case their 2 cores will consume 8W for the same 130 throughput, wich is 62.5% better perf/Watt.

Their SMT-less core has 115 performance at 100% power. Their possible HT version would have 130 performance at 120% power. So HT does not bring any throughput increase at isopower. And that's not even apples to apples comparison, pretty much nobody needs pure throughput at desktop or mobile - what they need is MT-performance and biggest factor to have it is to have best possible ST-performance to scale other threads too.
 
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Abwx

Lifer
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Their SMT-less core has 115 performance at 100% power.

You mean that the SMTed core has 115% of the power at same perf.?.
Because 15% better perf at same power is not possible, this would amount to comparison with a SMT core using roughly 35% more power at same perf.

In wich case those 35% can be used to clock a SMT less core 15% higher at same power.


Their possible HT version would have 130 performance at 120% power. So HT does not bring any throughput increase at isopower. And that's not even apples to apples comparison, pretty much nobody needs pure throughput at desktop or mobile - what they need is MT-performance and biggest factor to have it is to have best possible ST-performance to scale other threads too.

If its perfs are 130 at 120% of the power then perf will be 120 at 100% of the power.

Eventually they removed SMT for other reasons that stated, perhaps that it doesnt bode well with a uarch using hybrid cores and that it doesnt cost that much to replace a SMT thread by a relatively small core.
 

naukkis

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You mean that the SMTed core has 115% of the power at same perf.?.
Because 15% better perf at same power is not possible, this would amount to comparison with a SMT core using roughly 35% more power at same perf.

In wich case those 35% can be used to clock a SMT less core 15% higher at same power.
Just like Intel demonstrated, they have 115% single-thread performance at same power with their single-thread optimzed core as SMT-core running one thread. At that same power level SMT-cores both combined threads execute 130% instructions compared to that same core with single thread - performance from two combined threads aren't directly comparable to single threads as splitting work to two threads will decrease efficiency. They even know that and put it that way that it's technically correct - newer compare multiple threads performance to single thread directly.
 
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