Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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DavidC1

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From Digitimes Asia:
Some more confirmation that Lunar Lake is delayed: Lunar Lake not shipping until September instead of expected June.
Ok, but Digitimes is a hit-and-miss. Was it ever delayed or is it like the Meteorlake GPU tile, N5 or N3 question? It was never N3, but outlets reported that they had problems and they had to use N5 or some nonsense.

@AMDK11
Regarding Lion Cove, Intel, emphasizing the division of the schedule into separate for ALU and separate for FPU, shows P-Core graphics with 10x ALU and 8x FPU for future generations :D

That just tells me that they are expanding without much thought. Like 8x branch capability. All that for 14% gain?
 

DavidC1

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Also, some of these factors like design & hardware complexity, increased die area and power usage might also have contributed to the decision. Can't confirm.

It appears, RU rumor is gonna stay just a rumor after all. :coldsweat:
If you listen to what @Exist50 has been saying then he expects it post-2026 or even later. That doesn't sound like a project without significant issues.

Yea I hope the E core team continues to execute. Arctic Wolf = 30% and in two years another 30% gain? Now we're threatening not just the P core team from both companies, but Apple.
 

Hulk

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Well wouldn't it be just as performant single thread as doesn't single thread mean only 1 core? Or does single thread also mean more than 1 core, but limited amount beyond 1 core for SMT?
Almost nothing outside of ST benchmarks are single thread. But, there are applications that will spawn quite a few threads but only really put pressure on 2 or 3, or maybe 4 or 5. That is what I mean by ST performance. If these "supporting threads" are carried by Raptor strength Skymont cores we might only need 4 or 6 Lion Cove cores.

The E's don't look to be the weaklings they used to be.
 

Hulk

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Also, one nice thing about the Intel hybrid architecture is that we can test various configurations. 6+12 or 8+8 in different applications and see if the result is what we expect?

Let's do some of that once ARL arrives and see how the various configurations perform. We could each take a different software application and test a few configurations and then compile in a spreadsheet.
 

tamz_msc

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Regarding the lack of HT, now I just run my Tiger Lake with HT off. Everything feels snappier - especially initial startup. Like it is much faster to settle down after a fresh Windows boot.

App launch time has decreased, even responsiveness within apps has noticeably improved.

I have little doubt that Lion Cove will feel even more responsive than Raptor Lake, despite the lack of HT and "only" a 14% IPC uplift.
 

dullard

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May 21, 2001
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The E's don't look to be the weaklings they used to be.
That, and the impression that many people stick with of the E cores is from initial reviews before any software was coded to differentiate the cores. It doesn't take much effort to specify the proper core to run on when starting a thread. And no one knows better than the programmer what emphasis the thread should have. Each day when more software comes out or older software is upgraded, the E cores get utilized better and better.
 

DrMrLordX

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Afaik 8+32 was cancelled in favor of bigger NPU on ARL-R.

Ugh why. You don't need an NPU on desktop skus. They have discreet graphics to cover that base, unless it's some kind of latency-sensitive AI workload.

Spamming even more e-cores (regardless of how good they are compared to previous-gen e-cores) isn't exactly the best idea because Amdahl's Law does bite you in the end, but sacrificing die area to an NPU seems even less useful.
 

ondma

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Almost nothing outside of ST benchmarks are single thread. But, there are applications that will spawn quite a few threads but only really put pressure on 2 or 3, or maybe 4 or 5. That is what I mean by ST performance. If these "supporting threads" are carried by Raptor strength Skymont cores we might only need 4 or 6 Lion Cove cores.

The E's don't look to be the weaklings they used to be.
How about gaming? Are games going to finally be able to use the E cores?
 

TESKATLIPOKA

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More performance, less power. Why wouldn't you want that. Unless you fall into the false belief that you want P cores for things like gaming.
For maxing that CPU 6P+24E you would need 30 threads, with HT It's 36. How many desktop Apps can use that many? Actually, more users would be hurt by dropping 2 P cores than having extra E-cores.

And P-cores are faster for gaming than E-cores, that's a fact.

If ARL does not have HT, then 8P+24E for 32 threads is my limit for desktop. Anything more is in my opinion server(cloud) market.
 
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Hulk

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As for

For maxing that CPU 6P+24E you would need 30 threads, with HT It's 36. How many desktop Apps can use that many? Actually, more users would be hurt by dropping 2 P cores than having extra E-cores.

And P-cores are faster for gaming than E-cores, that's a fact.

If ARL does not have HT, then 8P+24E for 32 threads is my limit for desktop. Anything more is in my opinion server(cloud) market.
Good points. You might be right. That's why if some of us get ARL it would be interesting to do some testing.
 

AMDK11

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That just tells me that they are expanding without much thought. Like 8x branch capability. All that for 14% gain?
On average +14% IPC is without AVX512 and HT. The IPC curve of Zen 4 and Zen 5 includes AVX512 and probably SMT.

Going from ALU 5 to 6 is an increase of +20%.

We'll see how much ArrowLake will gain.
 
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inf64

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On average +14% IPC is without AVX512 and HT. The IPC curve of Zen 4 and Zen 5 includes AVX512 and probably SMT.

Going from ALU 5 to 6 is an increase of +20%.

We'll see how much ArrowLake will gain.
You are giving too much credit to ALU increase. Zen 5 has 50% more ALU units (4 to 6) and gets "only" ~16% IPC according to AMD's number (the only one we have so far). If it were that easy to simply slap on ALU/AGUs or execution ports and get "free" IPC, everyone would have a field day. It's super complicated dance of resources and power and has 100s of variables. It's basically a tradeoff every time.
 

CouncilorIrissa

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You are giving too much credit to ALU increase. Zen 5 has 50% more ALU units (4 to 6) and gets "only" ~16% IPC according to AMD's number (the only one we have so far). If it were that easy to simply slap on ALU/AGUs or execution ports and get "free" IPC, everyone would have a field day. It's super complicated dance of resources and power and has 100s of variables. It's basically a tradeoff every time.
Yes.
If unit and resource counts were all that mattered, then GLC would be far ahead of Persephone (Z4 core uarch), and it's on par.
 
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AMDK11

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You are giving too much credit to ALU increase. Zen 5 has 50% more ALU units (4 to 6) and gets "only" ~16% IPC according to AMD's number (the only one we have so far). If it were that easy to simply slap on ALU/AGUs or execution ports and get "free" IPC, everyone would have a field day. It's super complicated dance of resources and power and has 100s of variables. It's basically a tradeoff every time.
I deliberately used simplification. I just wanted to emphasize that the profits often do not even reach 50% of the amount of resources added.
 
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SiliconFly

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Core ultra 9 have higher base clock than 14900k.. wonder which node N3B or 20A ?🤔
Final nail in the coffin. So, we now have confirmation ARL-S desktop 8+16 has no HT anymore.

Thanks to Intel for getting rid of useless/issue prone HT in client!
 
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SiliconFly

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Rumoured to be N3B
ARL-S is rumored to be on N3B and ARL-H on 20A. Both nodes should be able to clock high enough if necessary as N3B is more mature now and 20A has BSPD.

Interesting times ahead... competition will be neck-to-neck on ST & will be a total wipe-out on 8+16 MT.