Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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Hulk

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Honestly, if Skymont is Raptor Cove from an IPC point of view, I don't see a lot of applications on the desktop that could use 8+32 (over 8+16) outside of CB benchmarking and DC. With Raptor Lake once all of the Raptor Cove physical threads are occupied there is a significant drop in performance on the Gracemont threads. We're looking at a nearly 50% IPC improvement from Gracemont to Skymont. It's massive.

If Lion Cove is +14% over Raptor Cove and can do 5.4GHz all-core and Skymont is delivered as promised Intel will be fine with ARL. More than fine actually. It looks like Intel and AMD have the tech, they just have to deliver it in a timely manner.
 

Geddagod

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Honestly, if Skymont is Raptor Cove from an IPC point of view, I don't see a lot of applications on the desktop that could use 8+32 (over 8+16) outside of CB benchmarking and DC. With Raptor Lake once all of the Raptor Cove physical threads are occupied there is a significant drop in performance on the Gracemont threads. We're looking at a nearly 50% IPC improvement from Gracemont to Skymont. It's massive.

If Lion Cove is +14% over Raptor Cove and can do 5.4GHz all-core and Skymont is delivered as promised Intel will be fine with ARL. More than fine actually. It looks like Intel and AMD have the tech, they just have to deliver it in a timely manner.
Napkin math using 5.5GHz nT and 4.6 Ghz nT for LNC and SKMT suggests a ~20% uplift over RPL for INT workloads.
 

The Hardcard

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Honestly, if Skymont is Raptor Cove from an IPC point of view, I don't see a lot of applications on the desktop that could use 8+32 (over 8+16) outside of CB benchmarking and DC. With Raptor Lake once all of the Raptor Cove physical threads are occupied there is a significant drop in performance on the Gracemont threads. We're looking at a nearly 50% IPC improvement from Gracemont to Skymont. It's massive.

If Lion Cove is +14% over Raptor Cove and can do 5.4GHz all-core and Skymont is delivered as promised Intel will be fine with ARL. More than fine actually. It looks like Intel and AMD have the tech, they just have to deliver it in a timely manner.
If they get the power and thermals under control, an 8+32 might appeal to the low end workstation market. Especially if they can put it into a Mac Studio type box that is portable and quiet, but with enough power for say video, editors, and audio engineers, as well as others who could use that kind of oomph in an easy to move device.

Put in a 5080 GPU with the easy option of lower clocks so it also doesn’t need fans blasting, it will appeal to some.
 

Geddagod

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That napkin math is with SMT enabled on LNC or not?
Not enabled. I don't think we are getting SMT on ARL either...
If they get the power and thermals under control, an 8+32 might appeal to the low end workstation market. Especially if they can put it into a Mac Studio type box that is portable and quiet, but with enough power for say video, editors, and audio engineers, as well as others who could use that kind of oomph in an easy to move device.

Put in a 5080 GPU with the easy option of lower clocks so it also doesn’t need fans blasting, it will appeal to some.
Power, mem bandwidth, and sheer die size and cost all start becoming bigger and bigger issues...
 

SiliconFly

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Based on @Hitman928's chip area calculations, Skymont is ~40-50% the size of Lion Cove. So an 8+32 would be like 21-24 P-cores on one chip area-wise. Is that feasible? It would certainly be a MT monster.
The P core to E core ratio is close to 1:3. So, roughly 18-19. And yes, it'd be a monster. And very much suitable for HEDT (like threadrippers).
 
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Hulk

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6+24 would be only slightly larger area-wise than 8+16 and deliver nearly the same ST performance a a significant boost in MT now that the E's are so performant.
 
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dullard

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6+24 would be only slightly larger area-wise than 8+16 and deliver nearly the same ST performance a a significant boost in MT now that the E's are so performant.
I've been calling for that 6+24 solution for many years. One example:
...I think Intel is missing out on a potential multithreaded monster: 6 P cores, 24 E cores. Instead they went with 8 P Cores and 16 E cores. Both would use about the same amount of power and about the same amount of silicon area. But 6+24 would blow these away in multi-threaded applications.
 
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Wolverine2349

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6+24 would be only slightly larger area-wise than 8+16 and deliver nearly the same ST performance a a significant boost in MT now that the E's are so performant.

Well wouldn't it be just as performant single thread as doesn't single thread mean only 1 core? Or does single thread also mean more than 1 core, but limited amount beyond 1 core for SMT?
 

dullard

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Come on guys!!! Please don't give Intel any more ideas on how to span E cores. I could see 8+24, perhaps for (uggh) ARL-R, but I really would hate to see them delete P cores in order to include more E cores.
More performance, less power. Why wouldn't you want that. Unless you fall into the false belief that you want P cores for things like gaming.
 

Wolverine2349

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More performance, less power. Why wouldn't you want that. Unless you fall into the false belief that you want P cores for things like gaming.

Well more performant lower power P cores so no hybrid scheduling quirks and yes better for gaming for sure.

Maybe the e-cores become the new P cores anyways if the Austin team, is really doing that well and Israel design center is not sometime in a couple or few years???
 
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SiliconFly

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More performance, less power. Why wouldn't you want that. Unless you fall into the false belief that you want P cores for things like gaming.
How about 2P+40E? I can already hear @ondma screaming! :tearsofjoy:

Tbh, ST performance is king (even now). It's way more important than MT. More ST, much better. Even for mundane tasks like browsing or office apps.

A thought experiment. Imagine having 256 cores that run at 1x speed each or just 2 cores that run at 100x speed each. Every single app will do better on the 2 cores. Not just games, even browsers. They'll run at blinding speed.

Most of the people don't benefit fully from having tons of cores. It's mostly bragging rights. But almost everyone benefits from having very high ST. Higher ST rules!
 

Wolverine2349

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How about 2P+40E? I can already hear @ondma screaming! :tearsofjoy:

Tbh, ST performance is king (even now). It's way more important than MT. More ST, much better. Even for mundane tasks like browsing or office apps.

A thought experiment. Imagine having 256 cores that run at 1x speed each or just 2 cores that run at 100x speed each. Every single app will do better on the 2 cores. Not just games, even browsers. They'll run at blinding speed.

Most of the people don't benefit fully from having tons of cores. It's mostly bragging rights. But almost everyone benefits from having very high ST. Higher ST rules!

Yes agree assuming by single thread more than 1 core but not spammed with so many and thus too many cores.

Like 8-12 high performing cores on a single node is the sweet spot. Too bad it maxes out at 8 on a single node/die/ring bus/CCX from either company.

Best balance of multi thread and single thread and lightly threaded and finite threaded performance for consumer desktop and gaming.
 
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ondma

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From Digitimes Asia:
Some more confirmation that Lunar Lake is delayed: Lunar Lake not shipping until September instead of expected June.
This means LL laptops will miss the back to school sales rush for sure, and may have poor availability for the end of year holiday season.
Speculation is that it is due to poor yields on the TSMC N3B node.
Wonder what that means for ARL availability?? (rhetorical question, BTW) 5 or 6 months behind Zen 5 may not be such a stretch after all.
Yes, I know the article did not mention ARL specifically, but since the highest end chips are on the same node, and Intel has switched priority to LL, further delays to ARL definitely seem possible.
 

dullard

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From Digitimes Asia:
Some more confirmation that Lunar Lake is delayed: Lunar Lake not shipping until September instead of expected June.
This means LL laptops will miss the back to school sales rush for sure, and may have poor availability for the end of year holiday season.
Speculation is that it is due to poor yields on the TSMC N3B node.
Wonder what that means for ARL availability?? (rhetorical question, BTW) 5 or 6 months behind Zen 5 may not be such a stretch after all.
Yes, I know the article did not mention ARL specifically, but since the highest end chips are on the same node, and Intel has switched priority to LL, further delays to ARL definitely seem possible.
TSMC just started producing Lunar Lake tiles this Tuesday. There was absolutely no possible way they would be a June launch. The tiles can't be produced, shipped to Intel, assembled, tested, packaged, and shipped to OEMs in any quantity in a week and a half. No, it will be a Q3 2024 launch that has been reported for quite some time, not a Q2 launch in June.
 

dullard

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How about 2P+40E? I can already hear @ondma screaming! :tearsofjoy:

Tbh, ST performance is king (even now). It's way more important than MT. More ST, much better. Even for mundane tasks like browsing or office apps.

A thought experiment. Imagine having 256 cores that run at 1x speed each or just 2 cores that run at 100x speed each. Every single app will do better on the 2 cores. Not just games, even browsers. They'll run at blinding speed.

Most of the people don't benefit fully from having tons of cores. It's mostly bragging rights. But almost everyone benefits from having very high ST. Higher ST rules!
You hit a point of diminishing returns on the power/performance graphs. Pumping ~125 W / 2 = ~62.5 W into each of two P cores won't really get you much performance gains. That is, even if they could be cooled at that power (heck, it would be a lot worse at turbo power levels). At least from what I've seen in past chips (I can't predict future chips), the sweet spot is much closer to 6 P cores.

Plus, there are plenty of software programs that require 4 or 6 fast threads. Those might come to a crawl on a 2P+40E chip. But, there is a much smaller subset of software that needs more than 6 fast threads, but less than 9, and can't use the E cores efficiently. In fact, I can think of no software that fits that bill. That is why I like the 6 P core design for fast ST performance and fill the rest with as many E cores as is reasonable in the power budget for MT performance.
 

SiliconFly

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(Based on publicly available info. Not a leak)

Just came across this regarding Rentable Units. Sounds bad.

This was posted by Ian 2 years ago.

Screenshot 2024-06-22 at 03-03-23 What ever happened to VISC and the idea of 'combining' cores...png

Some background: Back in 2016, Ian wrote an AT article on Soft Machines VISC. Then, a few years ago, there were rumors that Intel is working on Rentable Units and it's based on its soft machines acquisition. Back in Oct 29, 2020, Intel did apply for a patent based on the same. But in 2022, Ian said that it got mothballed. No more news beyond that. Thats a serious concern.

Also, some of these factors like design & hardware complexity, increased die area and power usage might also have contributed to the decision. Can't confirm.

It appears, RU rumor is gonna stay just a rumor after all. :coldsweat:
 
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Henry swagger

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(Based on publicly available info. Not a leak)

Just came across this regarding Rentable Units. Sounds bad.

This was posted by Ian 2 years ago.

View attachment 101621

Some background: Back in 2016, Ian wrote an AT article on Soft Machines VISC. Then, a few years ago, there were rumors that Intel is working on Rentable Units and it's based on its soft machines acquisition. Back in Oct 29, 2020, Intel did apply for a patent based on the same. But in 2022, Ian said that it got mothballed. No more news beyond that. Thats a serious concern.

Also, some of these factors like design & hardware complexity, increased die area and power usage might also have contributed to the decision. Can't confirm.

It appears, RU rumor is gonna stay just a rumor after all. :coldsweat:
he is wrong lol
 

AMDK11

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Regarding Lion Cove, Intel, emphasizing the division of the schedule into separate for ALU and separate for FPU, shows P-Core graphics with 10x ALU and 8x FPU for future generations :D
 
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