Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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SiliconFly

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Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL?
Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?
Very much possible.

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.
Best case they might even add another 15% IPC. LNC in ARL isn't just an updated LNC in LNL. They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Also remember, LNC in LNL isn't allowed to stretch it's legs due to power/thermal constraints. Not so in case of ARL. Some free bonus there too.

We may just receive 2% to 3% IPC uplift (over LNC in LNL) like you said. Or we may end up with a massive 30% uplift. Who knows? We can only speculate until they say so.
 
Jun 4, 2024
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Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL? Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.
I am guessing 2-3% benefit too, considering for all the issues LP E cores in meteor lake had, they were still only 5% average slower than regular E cores.

Lion Cove on meteor lake will have faster/higher power fabric, faster ring bus, more cache, at a minimum.
 

eek2121

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Aug 2, 2005
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Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL? Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.
What I think we'll get:
More,
Higher L1/L2 bandwidth,
SMT,
Higher clocks

How much faster Arrow Lake is will depend largely on any clock regressions. Note that current claims about clock regressions are rumors and nothing more. Single core clocks probably won't regress much, if at all since they aren't power limited to begin with (yes, even on Intel processors lol). All core clocks WILL likely dip unless the process makes up for it.
Very much possible.


Best case they might even add another 15% IPC. LNC in ARL isn't just an updated LNC in LNL. They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Also remember, LNC in LNL isn't allowed to stretch it's legs due to power/thermal constraints. Not so in case of ARL. Some free bonus there too.

We may just receive 2% to 3% IPC uplift (over LNC in LNL) like you said. Or we may end up with a massive 30% uplift. Who knows? We can only speculate until they say so.
I think we are likely to see a 15-20% single core uplift, depending on the workload, depending on whether clocks drop, and by how much. This is based on the changes I mentioned above. Multicore uplift should be significantly higher, possibly 40-50%, as Intel has massively improved their E-cores and power consumption should be driven down considerably via process improvement.

A lot of it is going to come down to those power numbers. Unless they change it (AGAIN), Intel is dropping power limits to be more competitive with AMD parts. I believe the quoted PL2 number for Arrow Lake was 177W. AMD is currently 230W for their power limit, but TDP is capped at 170W. In addition, the cores would normally need more power, though if they can release on Intel 20A/18A/TSMC N3* that should mitigate most of the power consumption, if not all of it. There are some perf/watt improvements in the architecture, however, that should help. Intel went over some of it during the Computex talks.
 
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Magio

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May 13, 2024
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Hopefully the fact they're putting 4 P cores in a 15W (+2W memory) SKU speaks to improved power consumption characteristics for Lion Cove compared to prior P core designs from Intel. I don't expect all cores on LNL to be able to truly stretch their legs within that power limit of course, but if they can even function adequately not too far from it that would be a bigger gen-on-gen improvement than even the IPC gains from Skymont.

IPC is of course important but power consumption and thermals have been far more pressing issues in recent Intel designs.
 
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One thing I don't really understand is the uArch Skymont vs uArch Raptor Cove comparison. 1.2x performance at equal power and 40% lower power at equal performance: does anyone know if they're controlling for process node? Because Intel also cites 20-80% PPW at low power for Skymon vs Lion Cove, and those are on the same node; since Lion Cove is more efficient than Raptor Cove, the advantage for skymont over raptor cove must be greater, unless they're discussing different power envelopes.
 
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Geddagod

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Why? If you stop at 5W in this graph it’s fine. Crestmont perf/watt curve is good, I don’t see a reason why it’d change dramatically in Skymont.
Ye, you're right. I take that back. Didn't actually pay attention to the low end of that graph.
One thing I don't really understand is the uArch Skymont vs uArch Raptor Cove comparison. 1.2x performance at equal power and 40% lower power at equal performance: does anyone know if they're controlling for process node?
Doubt it.
Because Intel also cites 20-80% PPW at low power for Skymon vs Lion Cove, and those are on the same node; since Lion Cove is more efficient than Raptor Cove, the advantage for skymont over raptor cove must be greater, unless they're discussing different power envelopes.
Probably.
Best case they might even add another 15% IPC.
Bruh
LNC in ARL isn't just an updated LNC in LNL.
It is
They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.
Bro....
Or we may end up with a massive 30% uplift. Who knows?
Lmao
 

Hulk

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Oct 9, 1999
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One thing I don't really understand is the uArch Skymont vs uArch Raptor Cove comparison. 1.2x performance at equal power and 40% lower power at equal performance: does anyone know if they're controlling for process node? Because Intel also cites 20-80% PPW at low power for Skymon vs Lion Cove, and those are on the same node; since Lion Cove is more efficient than Raptor Cove, the advantage for skymont over raptor cove must be greater, unless they're discussing different power envelopes.
Lion Cove and Skymont have been engineered very specifically. From Intel rep. talk I have been transcribing. Parenthesis are notes to myself.

So one of the questions this morning is, “Hey your last gen you had two low power ecores and now there are four E cores?” That's true because these cores scale way down low where the low power island did in in Meteor Lake. So we cover that use case (extremely low power) and we've also doubled the core count versus last year's low power Island so now we can get the E core benefit too (better MT performance) and as you scale up in performance we get a lot more out of all of these cores computationally. That allows us to simplify the design, reduce the area of the die, and essentially collapse two features (low, low power, and low power high performance) into one because these are simply more capable. If we look at them together, one thing I want to highlight here is that these cores are designed to cover a full range of power and frequency.



We do what we call what I call bottom up scheduling so the E core is first in scheduling, We want workloads to go to the most efficient core first, and then when the workload is too significant for that four core cluster to handle, only then do we move it upwards into the P core. But remember we do have Thread Director, we have intelligence scheduling technology so yes it is absolutely possible to jump straight to the P core first.



At the low end (of the power spectrum) the E cores are actually somewhere between 20 and 80% more performant (at iso power) than the P core, and at the high end kind of the opposite is true. You get 50 plus percent more performance out of the P core versus the E core. So this (full power/performance) range is why we do P cores and E cores (The E cores have a better performance/power ratio at low power and the P cores have a better performance/power ratio at high power). This range is why you can remove technologies like SMT, which have been around for forever, because now we have core technologies that can bring that single thread and multi-thread performance that was previously only deliverable through a technology like hyperthreading.
 
Jun 4, 2024
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Lion Cove and Skymont have been engineered very specifically. From Intel rep. talk I have been transcribing. Parenthesis are notes to myself.

So one of the questions this morning is, “Hey your last gen you had two low power ecores and now there are four E cores?” That's true because these cores scale way down low where the low power island did in in Meteor Lake. So we cover that use case (extremely low power) and we've also doubled the core count versus last year's low power Island so now we can get the E core benefit too (better MT performance) and as you scale up in performance we get a lot more out of all of these cores computationally. That allows us to simplify the design, reduce the area of the die, and essentially collapse two features (low, low power, and low power high performance) into one because these are simply more capable. If we look at them together, one thing I want to highlight here is that these cores are designed to cover a full range of power and frequency.



We do what we call what I call bottom up scheduling so the E core is first in scheduling, We want workloads to go to the most efficient core first, and then when the workload is too significant for that four core cluster to handle, only then do we move it upwards into the P core. But remember we do have Thread Director, we have intelligence scheduling technology so yes it is absolutely possible to jump straight to the P core first.



At the low end (of the power spectrum) the E cores are actually somewhere between 20 and 80% more performant (at iso power) than the P core, and at the high end kind of the opposite is true. You get 50 plus percent more performance out of the P core versus the E core. So this (full power/performance) range is why we do P cores and E cores (The E cores have a better performance/power ratio at low power and the P cores have a better performance/power ratio at high power). This range is why you can remove technologies like SMT, which have been around for forever, because now we have core technologies that can bring that single thread and multi-thread performance that was previously only deliverable through a technology like hyperthreading.
Nice thanks
 

DrMrLordX

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edit: somehow a quote wandered over from the Zen5 thread and I'm not sure how it got here. Either that or I was in an off-topic conversation so I've deleted my response.

6+8 is both TSMC and Intel.

Huh, how will Intel handle sourcing the 6+8 tile from different foundry companies? Are they going to mix and match within the same SKU or parcel them out to different SKUs based on the source foundry?
 
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Elfear

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Best case they might even add another 15% IPC. LNC in ARL isn't just an updated LNC in LNL. They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Also remember, LNC in LNL isn't allowed to stretch it's legs due to power/thermal constraints. Not so in case of ARL. Some free bonus there too.

We may just receive 2% to 3% IPC uplift (over LNC in LNL) like you said. Or we may end up with a massive 30% uplift. Who knows? We can only speculate until they say so.

Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...
 
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SiliconFly

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Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...
Interesting. Someone just forgot about the recent Crestmont to Skymont.

Things happen. Both with AMD & Intel. We can never be sure of what to expect in this climate.
 

Ghostsonplanets

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Huh, how will Intel handle sourcing the 6+8 tile from different foundry companies? Are they going to mix and match within the same SKU or parcel them out to different SKUs based on the source foundry?
From what I know, N3B 6+8 should be the highest volume at first, with 20A being lower volume. 20A ramp up later, with (maybe), getting the lions share of 6+8 die volume.

And 6+8 20A die is exclusively Desktop. Mobile is only 6+8 TSMC N3B.
 
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The odds of that are like 0.01%. Realistically a 2-5% above Lunar Lake’s variant of Lion cove is best case scenario for ARL-S.

The only way I can see it exceeding that is if they somehow reduce latency significantly with the SoC tile designed for desktop.

Edit: Why am I being downvoted / reported for a benign statement?
I agree, expecting 2x performance gain by moving from low power design to high power design seems wildly optimistic. If they include HT, I could see MT gaining that extra 20%, but IPC for single threaded workloads isn't changing by an additional 15%.
 

Hulk

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Has a 15-30% IPC increase ever happened on the same basic core design? Genuinely asking here. That would be like the same IPC increase we saw from RWC --> LNC on the low-end or Cypress Cove to LNC on the high-end. That seems so far outside the realm of possible...
No. We used to call that a "tick." 5% is all we ever saw and it was usually due to very minor core/cache/memory subsystem changes.

Golden Cove to Raptor Cove would have been a tick back in the tock-tock days. Large L2 cache, more cores, and a process stepping.
 
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Hulk

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Okay, that answers my question: they won't mix & match within the same SKU. Which makes sense.
Could you imagine the mess that would cause? Kind of like SSD manufacturers using different NAND vendors. "Hey, did you get the Intel 20A or the TMSC N3B CPU tile on your ARL? I hear the memory controller is generally better on the Intel node but the TMSC clocks higher with less voltage. I'm gonna return mine and try again."
 

Joe NYC

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Jun 26, 2021
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Interesting. Someone just forgot about the recent Crestmont to Skymont.

Things happen. Both with AMD & Intel. We can never be sure of what to expect in this climate.

It is much easier to increase IPC when starting from low IPC base (previous gen E-Cores) than from a much higher base (previous gen P-Cores)

Especially when given extra transistors, extra die area, extra power budget.
 
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DrMrLordX

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Could you imagine the mess that would cause? Kind of like SSD manufacturers using different NAND vendors. "Hey, did you get the Intel 20A or the TMSC N3B CPU tile on your ARL? I hear the memory controller is generally better on the Intel node but the TMSC clocks higher with less voltage. I'm gonna return mine and try again."
Apple did it years ago with modems. They didn't just use different processes, they used entirely different OEMs (Intel and Qualcomm). That was quite a fiasco.
 

FlameTail

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Screenshot_20240611_142947_YouTube.jpg
LNL has 3 display pipes. One would be used for internal display of laptop, meaning two remain for the external display.

So Lunar Lake laptops can only drive 2 external displays?