Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



Clockspeed.png
 

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Wolverine2349

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Do you have a link to the area estimates? The L2 area of the LNC cores aren't as clear to me based on the image Intel put out.

Edit: To add, in LNL, the P-cores have 2.5 MB of cache each while the E-cores have 4 MB shared (I included 1 MB worth per die in the area comparison). That makes me doubt that the E-core to P-core ratio shrinks when excluding L2 cache. Most likely, the 1:3 comparison was including L2 in the P-cores but excluding it in the E-cores. That would get you to about a 1:3 ratio but isn't a valid comparison.


I had forgotten about that the L2 cache. Then my hopes of a buying a Core Ultra 275K or 285K and disabling P cores and having an all Skymont core 12-16 P core Raptor Lake equivalent for homogenous non-hybrid arch CPU probably not reality.

Shared 4MB L2 per 4 e-core cluster where each P core has 2.5MB. So e-cores latency will be crippled.

Kind of like how Zen 4C has equal IPC to Zen 4 and Zen 5C will have equal IPC to Zen 5, but much less cache and clocks so real world performance across the board not near as good.

Oh well my hopes probably dashed for this Fall.

But Intel could put maybe more L2 cache per Skymont core on a dedicated die without clusters for better latency if they were intended to be Raptor Cove replacement in all work loads. But unfortunately at least their design initially they are intended for hybrid arch not to be on their own yet,

Though long term Intel can use these better cores and tune them and make them the new P cores. But unfortunately unlikely they can make that design for the great latency and L2 changes by this Fall.
 

SiliconFly

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Mar 10, 2023
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Considering all the changes/upgrades LNC has received over previous uarchs, none of them seem to standout (performance wise). There are no killer upgrades that are awe-inspiring. Will LNC bring in enough ST perf uplift in ARL? Hard to say at this point. And all the info published by the Intel P core team aren't inspiring either. :(

Has Intel's P core hit it's evolutionary limit? Should Intel just axe the Israel Design Center?
 

The Hardcard

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Oct 19, 2021
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I had forgotten about that the L2 cache. Then my hopes of a buying a Core Ultra 275K or 285K and disabling P cores and having an all Skymont core 12-16 P core Raptor Lake equivalent for homogenous non-hybrid arch CPU probably not reality.

Shared 4MB L2 per 4 e-core cluster where each P core has 2.5MB. So e-cores latency will be crippled.

Kind of like how Zen 4C has equal IPC to Zen 4 and Zen 5C will have equal IPC to Zen 5, but much less cache and clocks so real world performance across the board not near as good.

Oh well my hopes probably dashed for this Fall.

But Intel could put maybe more L2 cache per Skymont core on a dedicated die without clusters for better latency if they were intended to be Raptor Cove replacement in all work loads. But unfortunately at least their design initially they are intended for hybrid arch not to be on their own yet,

Though long term Intel can use these better cores and tune them and make them the new P cores. But unfortunately unlikely they can make that design for the great latency and L2 changes by this Fall.
i’m not clear why you would want to disable the P cores. In addition to building an effective E core, this generation appears to be fixing all the previous scheduling issues between P and E.

if Intel has its act together even half as much as it appears to, you gain virtually zero by disabling cores.
 

SiliconFly

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Mar 10, 2023
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i’m not clear why you would want to disable the P cores. In addition to building an effective E core, this generation appears to be fixing all the previous scheduling issues between P and E.

if Intel has its act together even half as much as it appears to, you gain virtually zero by disabling cores.
For example, take ARL-H 6P+8E. The Skymont cores are connected to L3 which offers more performance than the ones in Lunar Lake. And if we take only the performance of those 8 E cores (with the 6 P cores disabled), thats more than sufficient performance for a lot of people for day-to-day usage. Additionally we get a mind-boggling added bonus of extreme battery life. Probably upto 48 hours of casual use. Just sayin'.

Sadly, the LNC P cores aren't what many expected it to be.
 
Jun 4, 2024
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For example, take ARL-H 6P+8E. The Skymont cores are connected to L3 which offers more performance than the ones in Lunar Lake. And if we take only the performance of those 8 E cores (with the 6 P cores disabled), thats more than sufficient performance for a lot of people for day-to-day usage. Additionally we get a mind-boggling added bonus of extreme battery life. Probably upto 48 hours of casual use. Just sayin'.

Sadly, the LNC P cores aren't what many expected it to be.
We’ll see how lnc performs in arrow lake
 
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eek2121

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Does anyone know when we are actually getting some sku's? These things must be many months away if we don't even have that.
Arrow Lake or Lunar Lake? Lunar Lake should begin showing up in September. Arrow Lake won't realistically be available before 2025. Some speculate that Arrow Lake will launch at CES, but unless Intel really has knocked one out of the park with it (possibility), it will likely "launch" in Q4 with decent availability in 2025.
No Intel chip designers have explicitly stated that LNC in ARL will have HT. Some of the things they said kinda implies that ARL may get HT. Even I think it will. But Intel hasn't confirmed it yet.

And about HT, the P core designer said it in very high clarity the same thing I've been saying all along. HT kicks in and gives the performance increase only after all physical cores gets fully saturated during heavy multi-threaded workloads. And imho, this situation is not useful for most consumers and completely useless when there are plenty of E cores. HT is archaic and should just die.


4.6GHz is the best leak we've had till now.


In a month or two since they're targeting a sep launch.
They have, just not on the record. We can agree to disagree, however, and we'll find out soon at any rate.

They've been playing with some really interesting stuff (including things not mentioned here/in their videos) and it actually kind of makes me want to get back into hardware design/development (AMD and other companies avoiding CMT is another reason, almost completely unexplored area IMO). That is the thing that really kills me with ALL tech companies. Get rid of the corporate nonsense and you see some amazing and talented engineers behind it all. The corporate attitude limits that talent in many different ways, and even things like big wins in the engineering department can be completely hidden by corpspeak, especially for publicly traded companies

NOTE that if you ever did want to get into chip design, it is super cheap (and 'relatively' accessible assuming you can learn the foundational stuff). Forget 7nm/5nm/3nm/2nm, you can build stuff on much older processes for super cheap...I even remember a guy building a fab in his garage (something like 10um, a far cry from Intel 18a, but still). You can even breadboard a really basic chip, and it is a lot of fun. I can provide recommendations if you need a place to get started.
 

SiliconFly

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Arrow Lake or Lunar Lake? Lunar Lake should begin showing up in September. Arrow Lake won't realistically be available before 2025. Some speculate that Arrow Lake will launch at CES, but unless Intel really has knocked one out of the park with it (possibility), it will likely "launch" in Q4 with decent availability in 2025.

They have, just not on the record. We can agree to disagree, however, and we'll find out soon at any rate.

They've been playing with some really interesting stuff (including things not mentioned here/in their videos) and it actually kind of makes me want to get back into hardware design/development (AMD and other companies avoiding CMT is another reason, almost completely unexplored area IMO). That is the thing that really kills me with ALL tech companies. Get rid of the corporate nonsense and you see some amazing and talented engineers behind it all. The corporate attitude limits that talent in many different ways, and even things like big wins in the engineering department can be completely hidden by corpspeak, especially for publicly traded companies

NOTE that if you ever did want to get into chip design, it is super cheap (and 'relatively' accessible assuming you can learn the foundational stuff). Forget 7nm/5nm/3nm/2nm, you can build stuff on much older processes for super cheap...I even remember a guy building a fab in his garage (something like 10um, a far cry from Intel 18a, but still). You can even breadboard a really basic chip, and it is a lot of fun. I can provide recommendations if you need a place to get started.
I used to play around with microprocessors & micro-controllers in the early days. 8051 was my favorite. Even made a 80386DX addon board for a h/w based debugger. Good old times. And I think you're talking about tiny tapeout.
 
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Wolverine2349

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i’m not clear why you would want to disable the P cores. In addition to building an effective E core, this generation appears to be fixing all the previous scheduling issues between P and E.

if Intel has its act together even half as much as it appears to, you gain virtually zero by disabling cores.

Well is every issue perfect even with WIN10. It's still heterogeneous arch and can all game software be accounted for?

Isn't some software still not play nice with heterogeneous arch?

Supposedly every issue was fixed with 13th and 14th Gen scheduling yet Star Citizen and Elden Ring and some Wong game had issues.

I want best Raptor Lake 12 to 16 all P core equivalent homogeneous arch on single die for best set and forget gaming solution of all games all types past 15 to 20 years and furure games as well.

Will heterogeneous arch with Arrow Lake provide that unlike 13th and 14th Gen?
 

SiliconFly

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That makes a little more sense. But the last time it was described to me what SMT required from core area, it didn't seem like a huge deal.
The Intel P core designer stated clearly that if the HT structures are physically present in LNC and enabled, it uses more power. Thats one of the key reasons, LNC doesn't include HT in LNC. I think in LNL, LNC doesn't even include the HT related transistors.
 

Thunder 57

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14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed unless it's all a big like akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally power cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.

Well put. Much more interesting times these days in the CPU world than GPU world.
 
Jun 4, 2024
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14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed unless it's all a big like akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally power cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.
Well put. Both companies are doing amazing work. Glad to see Intel back (provided they deliver what the promised in September)
 

DrMrLordX

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The Intel P core designer stated clearly that if the HT structures are physically present in LNC and enabled, it uses more power.

It'd be interesting to see what that power delta is in "real world" usage scenarios. The e-cores should be solely engaged often enough that it seems like P-cores having HT wouldn't be a big issue. But I could be very wrong.

Thats one of the key reasons, LNC doesn't include HT in LNC. I think in LNL, LNC doesn't even include the HT related transistors.

Does that mean that Arrow Lake-S will include those transistors?
 

Bouowmx

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Nov 13, 2016
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Confirm my understanding of the latest lakes?

Desktop:
2024-5: Arrow Lake 8+16, TSMC 3/Intel 20A
2025-6: Arrow Lake Refresh 8+32, same process?
2026-7: Nova Lake, Royal Core?

Mobile:
2024-5: Lunar Lake and Arrow Lake, TSMC 3/Intel 20A
2025-6: Panther Lake (covering Lunar Lake's segments as well), Intel 18A
2026-7: Nova Lake, Royal Core?
 

Hitman928

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The comparison had it very clearly labelled. LNC vs SKT both with cache. And then LNC vs SKT both without cache. The first one was a bit rough due to some issues with the images i guess. The second one has better comparisons with hi res images and more accurate/revised results which put it at 1:3 exact (without cache for both).

I tried to locate it for a while without much success. But will keep trying...


Six cores are kinda okay-ish. But quad cores? Oh god!

If I compare the E-core without L2 cache to the P-core with L2 cache, I get appx. a 1:3 ratio (1.5 mm2 vs 4.25 mm2). That's the only way you can get to that ratio based upon the image shown previously.
 

ondma

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Confirm my understanding of the latest lakes?

Desktop:
2024-5: Arrow Lake 8+16, TSMC 3/Intel 20A
2025-6: Arrow Lake Refresh 8+32, same process?
2026-7: Nova Lake, Royal Core?

Mobile:
2024-5: Lunar Lake and Arrow Lake, TSMC 3/Intel 20A
2025-6: Panther Lake (covering Lunar Lake's segments as well), Intel 18A
2026-7: Nova Lake, Royal Core?
Desktop?
My understanding is that Arrow Lake 8+16 is TSMC and 6+8 is 20A
Nor sure what ARL=R will bring, but I think 8+32 is no longer on the roadmap.
Not sure after that. Is Royal Core even still a thing? Keller has been gone for quite some time from intel. Seems that if there is going to be a Royal Core it should be coming before 2026. Given the non-spectacular gains in Lion Cove, Intel seems to desperately need it.
 

SiliconFly

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It'd be interesting to see what that power delta is in "real world" usage scenarios. The e-cores should be solely engaged often enough that it seems like P-cores having HT wouldn't be a big issue. But I could be very wrong.



Does that mean that Arrow Lake-S will include those transistors?
Apparently, except me, many here are hoping ARL-S would actually include HT. Even I think it might have it cos the Intel P core designers kinda implied it. But I'm not a fan of HT. Good for servers, but bad for client. A vestigial appendage from a bygone era. Time to kill off HT completely in client ARL parts if you ask me.
 

TwistedAndy

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May 23, 2024
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Apparently, except me, many here are hoping ARL-S would actually include HT. Even I think it might have it cos the Intel P core designers kinda implied it. But I'm not a fan of HT. Good for servers, but bad for client. A vestigial appendage from a bygone era. Time to kill off HT completely in client ARL parts if you ask me.

In Lion Cove, Intel has changed the design approach from "Sea of Fubs" to the "Sea of Cells" and refactored the existing libraries:

It allows them to have a set of "knobs" to control which features will be physically presented in the silicon. In Lunar Lake, we will have the Lion Cove core without HT, AVX-512, and some other stuff.

But in ARL-S and, probably, ARL-H, we will have HT.
 

vanplayer

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May 9, 2024
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Not sure after that. Is Royal Core even still a thing? Keller has been gone for quite some time from intel. Seems that if there is going to be a Royal Core it should be coming before 2026. Given the non-spectacular gains in Lion Cove, Intel seems to desperately need it.
Confirm my understanding of the latest lakes?

Desktop:
2024-5: Arrow Lake 8+16, TSMC 3/Intel 20A
2025-6: Arrow Lake Refresh 8+32, same process?
2026-7: Nova Lake, Royal Core?

Mobile:
2024-5: Lunar Lake and Arrow Lake, TSMC 3/Intel 20A
2025-6: Panther Lake (covering Lunar Lake's segments as well), Intel 18A
2026-7: Nova Lake, Royal Core?
Royal core project has been shut down and reason is unknown.
 

Geddagod

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Dec 28, 2021
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Royal core itself is a rumor mostly spread by mlid. Thank god the imaginary project got shuttered cos it existed only in our minds. Actually, there weren't any credible leaks regarding the same.
Xino definitely has, and I don't remember for sure, but I think Raichu might have mentioned it here or there before too.
Why would you be thanking god that RYC, even if it was an imaginary project, got shut down? This would be pretty bad news. You are always complaining about how LNC seems like a dead end and now you are saying you don't want a fresh new core?
About the veracity of Royal Core, or any " radical next gen core pathfinding" teams being canned... who knows. But all I'm saying is that it wouldn't be too surprising. Just a couple days ago on the Intel subreddit there was talk of layoffs happening in DCAI. I wouldn't be surprised if this effected more than just that team- and cuts were being planned or in action at various parts of the company as well.
Though obviously should be hoping this doesn't happen.
Nor sure what ARL=R will bring, but I think 8+32 is no longer on the roadmap.
Imagine development of that got scrapped in favor for the new rumored SOC tile with a better NPU. Another victim of the AI hype.
Not sure after that. Is Royal Core even still a thing? Keller has been gone for quite some time from intel. Seems that if there is going to be a Royal Core it should be coming before 2026. Given the non-spectacular gains in Lion Cove, Intel seems to desperately need it.
2026-7: Nova Lake, Royal Core?

I agree with the sentiment, but Raichu has alluded before, and hell even MLID commented on this, that Panther cove was supposed to be a major (as in standard new p core) ipc bump but got pushed back. Panther Lake will apparently use Cougar Cove, Nova Lake panther cove, and the gen after that may use RYC, is my best guess.
14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy.
It's not the IPC I'm disappointed in the most, but what the perf/watt gains look like from both companies.
You can even breadboard a really basic chip, and it is a lot of fun
Me pulling an all nighter and struggling in my digital logic class to build a basic hex to 7 segment display circuit on my breadboard :cry:
Also, side note, istg Intel Quartus actually hates me, whenever I'm on a time crunch and need to create a waveform simulation it just crashes lol
TBF this perf/watt curve isn't very encouraging... maybe I am missing something.
he Lion Cove micro-op cache grew from 4,000 micro-ops in Redwood Cove to 5.250 in Lion Cove
Funny how this is still less than Zen 4
nd the OoO depth or instruction window was increased from 512 to 576 micro-ops.
Wonder why this didn't see a larger increase. IIRC, all other recent "major P-core updates" came with a much greater % ROB depth increase.
nd indeed the L2 online curve grows to 2.5MB on Lunar Lake and 3 MB on Arrow Lake
The power usage of these core private caches have to be insane. So much SRAM, running pretty fast... one has to wonder why Intel is buffing their core private caches so hard when you have AMD on the other hand staying with like 1MB of L2 per core lol.
I'm too pretty much convinced that MTL is more of a case study than a real product.
Nah
Hard to say. Panther Lake covers too many verticals unlike Lunar Lake. It'd be nice if it adopts LNL design, but it may not work well on higher core count parts like 8+16.
Only rumored to go up to 4+8+4
Thanks to IDC, RWC is horrible. An abomination if you ask me.
You have much too high standards. What makes you think RWC is that bad?
 
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Hulk

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Xino definitely has, and I don't remember for sure, but I think Raichu might have mentioned it here or there before too.
Why would you be thanking god that RYC, even if it was an imaginary project, got shut down? This would be pretty bad news. You are always complaining about how LNC seems like a dead end and now you are saying you don't want a fresh new core?
About the veracity of Royal Core, or any " radical next gen core pathfinding" teams being canned... who knows. But all I'm saying is that it wouldn't be too surprising. Just a couple days ago on the Intel subreddit there was talk of layoffs happening in DCAI. I wouldn't be surprised if this effected more than just that team- and cuts were being planned or in action at various parts of the company as well.
Though obviously should be hoping this doesn't happen.

Imagine development of that got scrapped in favor for the new rumored SOC tile with a better NPU. Another victim of the AI hype.



I agree with the sentiment, but Raichu has alluded before, and hell even MLID commented on this, that Panther cove was supposed to be a major (as in standard new p core) ipc bump but got pushed back. Panther Lake will apparently use Cougar Cove, Nova Lake panther cove, and the gen after that may use RYC, is my best guess.

It's not the IPC I'm disappointed in the most, but what the perf/watt gains look like from both companies.

Me pulling an all nighter and struggling in my digital logic class to build a basic hex to 7 segment display circuit on my breadboard :cry:
Also, side note, istg Intel Quartus actually hates me, whenever I'm on a time crunch and need to create a waveform simulation it just crashes lol

TBF this perf/watt curve isn't very encouraging... maybe I am missing something.

Funny how this is still less than Zen 4

Wonder why this didn't see a larger increase. IIRC, all other recent "major P-core updates" came with a much greater % ROB depth increase.

The power usage of these core private caches have to be insane. So much SRAM, running pretty fast... one has to wonder why Intel is buffing their core private caches so hard when you have AMD on the other hand staying with like 1MB of L2 per core lol.

Nah

Only rumored to go up to 4+8+4

You have much too high standards. What makes you think RWC is that bad?
Every micro architecture, no matter how well designed has bottlenecks. I would think that where some areas of the core aren't as improved as we might expect would be because they were less bottlenecked than other areas that received more attention. But of course at the end of the day Intel and only Intel has all of the answers and the simulations that point to why they did what they did.
 
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eek2121

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The Intel P core designer stated clearly that if the HT structures are physically present in LNC and enabled, it uses more power. Thats one of the key reasons, LNC doesn't include HT in LNC. I think in LNL, LNC doesn't even include the HT related transistors.
This is correct. People drastically overthink how much these chips are able to power down silicon. You can't power down 'part' of a core unless it is gated off in a way that allows you to do so. SMT has never been like this.
14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed unless it's all a big like akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally power cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.
Say it with me (Intel themselves said it): Lion Cove in Lunar Lake is not representative of future iterations/versions.

Arrow Lake will be > 14% faster than Raptor Lake. Significantly more power efficient as well.
 
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Hulk

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Oct 9, 1999
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Say it with me (Intel themselves said it): Lion Cove in Lunar Lake is not representative of future iterations/versions.

Arrow Lake will be > 14% faster than Raptor Lake. Significantly more power efficient as well.
Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL? Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.