Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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mikk

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Lunar Lake can scale upto 30W TDP, but it's also supposed to be used in fanless laptops.

What's the maximum TDP a fanless laptop would support?

It depends on the design and how big it is, I would say between 4-10W on a laptop. On LNL there is a 8W fanless option for Lunar Lake which is optional and this includes the on package RAM. Most designs should use 17W.
 

SiliconFly

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Just saw F1 race demo on Lunar Lake running at 60fps in 1080p. That means, LNL Battlemage with XeSS is on par with RTX 3050 mobile. This is serious gaming muscle. Covers almost all casual gamers (only excluding pro gamers who require high end cpus & tons of graphics power).

This also means third party discreet gpus aren't needed in mid-range laptops anymore.
 
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Triskain

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The Intel rep that said it will said otherwise. I think he knows better than random internet guy #567,345,124.
And what exactly did he say? Arrow Lake's Lion Cove will have more L2 Cache than Lunar Lakes's (3MB instead of 2.5), that just about covers the extent of the "differentiation" between them...
 

Hulk

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~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?
This is from the senior principal P core engineer and Intel slides.

HT adds 10% die area and additional power usage even when running ST.
 

inf64

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And what exactly did he say? Arrow Lake's Lion Cove will have more L2 Cache than Lunar Lakes's (3MB instead of 2.5), that just about covers the extent of the "differentiation" between them...
To be honest, the language he used was very vague so we don't know if there are more differences between the two.
 
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eek2121

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And what exactly did he say? Arrow Lake's Lion Cove will have more L2 Cache than Lunar Lakes's (3MB instead of 2.5), that just about covers the extent of the "differentiation" between them...
if i get bored i will dig up a video for part of it: according to Intel, Lion Cove is an "architecture" (not a "Core", an "architecture") that has "many" configurable options, including hyper-threading, that can be turned on and off as needed. Hyperthreading was turned off for Lunar Lake to save area and power. They said all of this on video, I'm sure you can find it.

For the more direct answer, it is coming soon. It wasn't communicated to me in any way I can show proof so you'll have to wait (or talk to an Intel rep).

Everything I've seen indicates Intel has actually done something few (any?) companies ever have, and I don't think they are being given enough credit. Based on their claims, they have made a silicon design that is highly configurable and easily portable between nodes/processes of multiple vendors. That is, Intel can quickly spin up a chip with Lion Cove cores in it on either TSMC or Intel processes, and on either N3/N5 or Intel 4/3/20A/18A with minimal effort. They can do this while also turning on/off or configuring major features.

In lunar lake, for example, L2 cache was cut down and also L1->L2 bandwidth, hyper-threading removed, AVX--512 is "supposedly" not present, and more. Lion Cove server cores will have none of those limitations, and desktop will be optimized around whatever makes sense for Arrow Lake.
 
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No, it won't.
We don’t know it won’t. It does seem unlikely, because Intel in Hulk’s linked presentation highlights HT benefits in thread-dense servers, but theoretically possible due to Lion Cove’s modularity. At Computex, Intel also said they would add HT where the performance benefits existed and power wasn’t as much of a concern.
 
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SiliconFly

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The Intel rep that said it will said otherwise. I think he knows better than random internet guy #567,345,124.
No Intel chip designers have explicitly stated that LNC in ARL will have HT. Some of the things they said kinda implies that ARL may get HT. Even I think it will. But Intel hasn't confirmed it yet.

And about HT, the P core designer said it in very high clarity the same thing I've been saying all along. HT kicks in and gives the performance increase only after all physical cores gets fully saturated during heavy multi-threaded workloads. And imho, this situation is not useful for most consumers and completely useless when there are plenty of E cores. HT is archaic and should just die.

4.6GHz is the best leak we've had till now.

Does anyone know when we are actually getting some sku's? These things must be many months away if we don't even have that.
In a month or two since they're targeting a sep launch.
 
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Hitman928

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~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

It’s 10% core area, probably not including L2 which means it ends up being like 0.3% of the compute die area for each of the four P-cores in LNL.
 
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if i get bored i will dig up a video for part of it: according to Intel, Lion Cove is an "architecture" (not a "Core", an "architecture") that has "many" configurable options, including hyper-threading, that can be turned on and off as needed. Hyperthreading was turned off for Lunar Lake to save area and power. They said all of this on video, I'm sure you can find it.

For the more direct answer, it is coming soon. It wasn't communicated to me in any way I can show proof so you'll have to wait (or talk to an Intel rep).

Everything I've seen indicates Intel has actually done something few (any?) companies ever have, and I don't think they are being given enough credit. Based on their claims, they have made a silicon design that is highly configurable and easily portable between nodes/processes of multiple vendors. That is, Intel can quickly spin up a chip with Lion Cove cores in it on either TSMC or Intel processes, and on either N3/N5 or Intel 4/3/20A/18A with minimal effort. They can do this while also turning on/off or configuring major features.

In lunar lake, for example, L2 cache was cut down and also L1->L2 bandwidth, hyper-threading removed, AVX--512 is "supposedly" not present, and more. Lion Cove server cores will have none of those limitations, and desktop will be optimized around whatever makes sense for Arrow Lake.
Right, I think the encouraging thing is that if HT is not included on Arrow Lake it is likely because not including HT was the better option for whatever power envelope Intel was targeting, rather than because they took a guess at the implications early in development and by the point the discovered HT was net benefit, it was too late.

Or even worse, that they tried to make HT work and couldn't.
 
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No Intel chip designers have explicitly stated that LNC in ARL will have HT. Some of the things they said kinda implies that ARL may get HT. Even I think it will. But Intel hasn't confirmed it yet.

And about HT, the P core designer said it in very high clarity the same thing I've been saying all along. HT kicks in and gives the performance increase only after all physical cores gets fully saturated during heavy multi-threaded workloads. And imho, this situation is not useful for most consumers and completely useless when there are plenty of E cores. HT is archaic and should just die.


4.6GHz is the best leak we've had till now.


In a month or two since they're targeting a sep launch.

Right, my 32 thread 5950x has 16 good threads, and 16 redacted ones that perform at best like 1/3rd the speed of the 16. This means that when making HPC apps, I have to be careful to design around that fact, or expect that things close to 16 cores not 32. Made worse by the fact that in some cases having HT enabled makes the 16 "good" threads individually slower. HT sucks and was a bandaid in the era when 32 cores on a die were unthinkable, never mind 144. We're past that, so HT needs to go away and Intel needs to drive core counts up by spamming Skymont.

I want to see a 64 core consumer part, with 8 lion cove for low-thread scenarios.

edit: Also, if Intel does ever get rentable units working, Chadmont will reach its final form, GigaChad.



No profanity in tech.


esquared
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Wolverine2349

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OMG I am so excited if true and 5GHz Skymont all core and Skymont also has the low latency of Raptor Cove and equal performance as Raptor Cove (HT disabled) across all workloads. My dream more than 8 strong cores for a homogenous non-hybrid arch on a single tile/ring bus/ CCX-CCD/die will be here in October.

Can just buy a Core Ultra 275K or 285K and have and disable Lion Cove cores and have a 12-16 all P core 5GHz Raptor Lake equivalent with HT disabled!!!! Here is to hoping!!
 
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SiliconFly

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It’s 10% core area, probably not including L2 which means it ends up being like 0.3% of the compute die area for each of the four P-cores in LNL.
Die area comparison between Lion Cove & Skymont is roughly 1:3 (without $). That means for every 10% area reduction in LNC with HT structures eliminated, represents roughly ~30% die area of Skymont. In other words, in a desktop part with 8 LNC cores, if we disable HT completely, we can easily have 2 additional Skymont cores for the die area saved. This additional 2 Skymont cores can easily give more performance than having HT.

HT is a dinosaur thats refusing to die. Hope there's a way to force kill it.

... that perform at best like 1/3rd the speed of the 16...
15 to 20% at best.

...not including HT was the better option for whatever power envelope Intel was targeting...
I didn't realise that HT is a power hog until the P core designed said so.

It's incredible,5G?
...5GHz Skymont all core... ...Here is to hoping!!...
I think those are more of theoretical limits. Real world SKT boost frequency should be in 4.xGHz range. I maybe totally wrong though.
 
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Hitman928

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Die area comparison between Lion Cove & Skymont is roughly 1:3 (without $). That means for every 10% area reduction in LNC with HT structures eliminated, represents roughly ~30% die area of Skymont. In other words, in a desktop part with 8 LNC cores, if we disable HT completely, we can easily have 2 additional Skymont cores for the die area saved. This additional 2 Skymont cores can easily give more performance than having HT.

Skymont is much closer to a 1:2 ratio with LNC.

HT is a dinosaur thats refusing to die. Hope there's a way to force kill it.

It still has its place for some server needs. Also, lower core count consumer CPUs can still greatly benefit from it. Overall, I'd kind of like to see it go away as well, but it is still useful for most consumers as long as Intel and AMD sell products with <= 6 cores.
 

Nothingness

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~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?
It's not impossible that it's10% (excluding caches area). I guess (I have no experience in that domain) if you want your second thread to perform well, while not sacrificing single thread performance, you have to increase some structures. And these structures can't be clock gated (and even less power gated) as they are the same as for ST, which means they will consume power.
 

SiliconFly

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Skymont is much closer to a 1:2 ratio with LNC.
Die shot comparison without cache puts it at 1:3. There were 2 different posts on twitter a while ago. And both showed close to 1:3. The second one (i don't have link) nailed it down to an exact 1:3.0x which was a revised figure actually. The most accurate i've come across.

It still has its place for some server needs. Also, lower core count consumer CPUs can still greatly benefit from it. Overall, I'd kind of like to see it go away as well, but it is still useful for most consumers as long as Intel and AMD sell products with <= 6 cores.
HT is awesome for servers. But not for clients. True it's beneficial for lower core count parts. But in this day and age, if anyone is buying quad core, they should be put in one of those cia blacksite prisons. I'll cover the transportation costs. Pinky swear.

To be more precise, Intel should just kill of HT in 6+8 & 8+16 & similar parts... and should try to increase E core counts instead with the saved die area.
 

Hitman928

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Die shot comparison without cache puts it at 1:3. There were 2 different posts on twitter a while ago. And both showed close to 1:3. The second one (i don't have link) nailed it down to an exact 1:3.0x which was a revised figure actually. The most accurate i've come across.


HT is awesome for servers. But not for clients. True it's beneficial for lower core count parts. But in this day and age, if anyone is buying quad core, they should be put in one of those cia blacksite prisons. I'll cover the transportation costs. Pinky swear.

To be more precise, Intel should just kill of HT in 6+8 & 8+16 & similar parts... and should try to increase E core counts instead with the saved die area.

Do you have a link to the area estimates? The L2 area of the LNC cores aren't as clear to me based on the image Intel put out.

Edit: To add, in LNL, the P-cores have 2.5 MB of cache each while the E-cores have 4 MB shared (I included 1 MB worth per die in the area comparison). That makes me doubt that the E-core to P-core ratio shrinks when excluding L2 cache. Most likely, the 1:3 comparison was including L2 in the P-cores but excluding it in the E-cores. That would get you to about a 1:3 ratio but isn't a valid comparison.
 
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SiliconFly

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Do you have a link to the area estimates? The L2 area of the LNC cores aren't as clear to me based on the image Intel put out.

Edit: To add, in LNL, the P-cores have 2.5 MB of cache each while the E-cores have 4 MB shared (I included 1 MB worth per die in the area comparison). That makes me doubt that the E-core to P-core ratio shrinks when excluding L2 cache. Most likely, the 1:3 comparison was including L2 in the P-cores but excluding it in the E-cores. That would get you to about a 1:3 ratio but isn't a valid comparison.
The comparison had it very clearly labelled. LNC vs SKT both with cache. And then LNC vs SKT both without cache. The first one was a bit rough due to some issues with the images i guess. The second one has better comparisons with hi res images and more accurate/revised results which put it at 1:3 exact (without cache for both).

I tried to locate it for a while without much success. But will keep trying...

You do realise that there are countries where a 6-core SKU costs more than monthly median income, right?
Six cores are kinda okay-ish. But quad cores? Oh god!