Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PPT1.jpg
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PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

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DavidC1

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Some think that 50% increase in LNL's IGP performance is a FLOP, but I think It's not necessarily bad. It would be more interesting, If we knew the exact TimeSpy score.
The reason the iGPU is being called disappointing is because it'll still be behind relative to what'll be the last-gen of the competition.

At 30-40W power levels, the 50% gain would be good. But at 15W it's very behind, and that's exactly where Intel is claiming 50% gain at 3DMark of all places will be happening.
TBH I wouldn't say MTL-U really exists given so few designs are out there.
We're still wondering and waiting for the mysterious BIOS update that makes Meteorlake tolerable.

MSI is continuing it with their Claw updates.
 

TESKATLIPOKA

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The reason the iGPU is being called disappointing is because it'll still be behind relative to what'll be the last-gen of the competition.

At 30-40W power levels, the 50% gain would be good. But at 15W it's very behind, and that's exactly where Intel is claiming 50% gain at 3DMark of all places will be happening.
There are no tests for LNL out, so you can hardly make any conclusions.
And It's not like this LNL is meant to be a competitor against Strix Point.

Does anyone know what score has 165U in Timespy at 15W? Then at least we can calculate LNL score.
 
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LightningZ71

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Mar 10, 2017
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?

LNL has an 8MB SLC and bumps the mem setup to L5x@8533. lmao.

No?
None of them are. They're limited by power, that's the defining trait of every RDNA3 part out there.
I stand corrected on the memory subsystem...

As for RDNA3, I'm specifically referencing Phoenix and Hawk, performance stops scaling closely with power draw rather quickly after 30-40W. Memory speed increases give decent performance increases in scenarios that are not limited by CPU core performance or internal GPU compute performance.
 
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Ghostsonplanets

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Does anyone know what score has 165U in Timespy at 15W? Then at least we can calculate LNL score.
Nobody has tested at this TDP range because there's barely any U based designs out there.

From NBC review, MTL U7 165U has a 2315 TimeSpy score at unspecified power consumption.

However, while Intel has specifically pointed out that the Lunar Lake design was a 17W one, the MTL U7 165U system TDP/operating power range wasn't disclosed.

If they're comparing LNL 17W x MTL-U unlocked power, that's a great result. But if it's 17W x 15W, that would be awful for LNL. Specially as, from MTL-H reviews, the Arc iGPU power curve is skewed towards the higher end and dies at low power (No tests with the new bios though).
 
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Ghostsonplanets

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I wonder where the mythical Core Ultra 5 115U is. It's on Intel Ark and appeared on Geekbench. But there's 0 designs out there.

I'm morbidly curious how a 2+4 CPU + 3 Xe Arc iGP would fare. Intel could sell these rejected dies for cheap just to do the funniest thing.
 
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Intel could sell these rejected dies for cheap just to do the funniest thing.
Even rejected, Intel wants to maintain a certain prestige for the Core Ultra brand name.

Check out the laptop designs for the U300 and their prices. Based on those, don't expect Core Ultra laptops, even lame ones, to be cheap for some time to come.
 

Ghostsonplanets

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Even rejected, Intel wants to maintain a certain prestige for the Core Ultra brand name.

Check out the laptop designs for the U300 and their prices. Based on those, don't expect Core Ultra laptops, even lame ones, to be cheap for some time to come.
If they do that, then they're missing an opportunity imo. They could increase market and mindshare with cheap Core Ultra and also attract customers to their own software stack ecosystem by having a cheap entry.

Even if U5 115U is a collection of rejected tiles, it still features a DX12.2 GPU and OpenVino/DirectML NPU, alongside with the battery life improvements. There's a lot of consumers, specially in poorer countries that would love having such capabilities.

I think it's important for Intel to get any win they can in face of increased competition and also solidify their headstart into the AI PC arena.
 

eek2121

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It is good to see more Meteor Lake ARC minis on the way. This AtomMan is pretty darned neat -


Set a frame cap on the games that are a little unbalanced and it will smooth right out. He could have used only rt reflections and XeSS with a 35-40fps cap in cyberpunk and it would have looked much better.
I would love to see them make the status LCD a touch screen OLED monitor and also make it as big as the case. Also if it doesn’t have mounting holds, they should add them.

Remove the stand, and these things would be perfect for a variety of use cases.
 

Wolverine2349

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Oct 9, 2022
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I have read Arrow Lake going to be 8 wide decoder improving from 6 wide 12th through 14th Gen?

Is Meteor Lake already 8 wide or is it still 6 wide? I have never found any answer on that googling it.
 

Hulk

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I have read Arrow Lake going to be 8 wide decoder improving from 6 wide 12th through 14th Gen?

Is Meteor Lake already 8 wide or is it still 6 wide?
We have very little info on MTL P cores but available evidence seems to point to only changes in the L2 in an effort to keep MTL P's on par with RTL P's due to the tile latency.

I'd think 8 wide decoder for Lion Cove is definitely happening.
 

Wolverine2349

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Oct 9, 2022
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We have very little info on MTL P cores but available evidence seems to point to only changes in the L2 in an effort to keep MTL P's on par with RTL P's due to the tile latency.

I'd think 8 wide decoder for Lion Cove is definitely happening.

Is 8 wide decoder why Arrow Lake will have better IPC than Raptor Lake but Meteor Lake being only 6 wide is why it had worse IPC and thus was made for only mobile and no desktop?

Is tile latency worse in general than the 10nm process node ring bus that 12th to 14th Gen are on?

Or is the tile just a new process node.

Cause Arrow Lake I have seen diagrams P cores seem to still be much bigger than e-cores and they are on same tile (like Meteor Lake excluding the ultra low power e-cores which desktop SKUs probably will not have) which is a big latency advantage over dual CCX/CCD greater than 8 core Zen 3 through Zen 5 parts?
 

AMDK11

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Jul 15, 2019
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Is 8 wide decoder why Arrow Lake will have better IPC than Raptor Lake but Meteor Lake being only 6 wide is why it had worse IPC and thus was made for only mobile and no desktop?

Is tile latency worse in general than the 10nm process node ring bus that 12th to 14th Gen are on?

Or is the tile just a new process node.

Cause Arrow Lake I have seen diagrams P cores seem to still be much bigger than e-cores and they are on same tile (like Meteor Lake excluding the ultra low power e-cores which desktop SKUs probably will not have) which is a big latency advantage over dual CCX/CCD greater than 8 core Zen 3 through Zen 5 parts?
MeteorLake is supposed to be energy efficient, so the lines between tiles are clocked lower and have higher delays, which in my opinion killed RedwoodCove's IPC increase.

LionCove has 24 microops from the decoder and uop cache compared to 14 from GoldenCove, which is an increase of 71%.

Likewise, there are more execution units, 18 compared to 12 in GoldenCove.
 

Hulk

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Oct 9, 1999
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Is 8 wide decoder why Arrow Lake will have better IPC than Raptor Lake but Meteor Lake being only 6 wide is why it had worse IPC and thus was made for only mobile and no desktop?

Is tile latency worse in general than the 10nm process node ring bus that 12th to 14th Gen are on?

Or is the tile just a new process node.

Cause Arrow Lake I have seen diagrams P cores seem to still be much bigger than e-cores and they are on same tile (like Meteor Lake excluding the ultra low power e-cores which desktop SKUs probably will not have) which is a big latency advantage over dual CCX/CCD greater than 8 core Zen 3 through Zen 5 parts?
I look at MTL as a test bed of sorts for Intel. Not only were they moving to tiles but also using a variety of nodes and their first crack at Intel 4. I think the point was to keep additional unknowns (like an overhauled P core) to an absolute minimum so that is why there were basically no architecture changes to the P cores. Get it up and running with as good performance as Raptor mobile with better efficiency and worry about better performance/efficiency with ARL and LL since they know the thing works.
 
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Markfw

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May 16, 2002
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I look at MTL as a test bed of sorts for Intel. Not only were they moving to tiles but also using a variety of nodes and their first crack at Intel 4. I think point was to keep additional unknowns (like a overhauled P core) to an absolute minimum so that is why there were basically no architecture changes to the P cores. Get it up and running with as good performance as Raptor mobile with better efficiency and worry better performance/efficiency with ARL and LL since they know the thing works.
My questions, do they have enough time to optimize performance and efficiency with these small changes, and such a timeline as they have to be able to compete ?
 
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H433x0n

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I look at MTL as a test bed of sorts for Intel. Not only were they moving to tiles but also using a variety of nodes and their first crack at Intel 4. I think point was to keep additional unknowns (like an overhauled P core) to an absolute minimum so that is why there were basically no architecture changes to the P cores. Get it up and running with as good performance as Raptor mobile with better efficiency and worry better performance/efficiency with ARL and LL since they know the thing works.
That was the goal but there’s 2 snags.

1) MTL was late. It was supposed to launch shortly after Phoenix.
2) ARL reuses MTL packaging. All of the negatives of that cursed tiled setup is inherited by ARL. The only kind of saving grace is that ARL-S has an SoC tile that’s more favorable to desktop but It’s still less than ideal.

It’s not a coincidence that LNL & PTL are dropping that packaging for a simpler implementation.
 
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