Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 297 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Tigerick

Senior member
Apr 1, 2022
686
576
106
PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Clockspeed.png
 

Attachments

  • PantherLake.png
    PantherLake.png
    283.5 KB · Views: 23,984
  • LNL.png
    LNL.png
    881.8 KB · Views: 25,456
Last edited:

Hulk

Diamond Member
Oct 9, 1999
4,380
2,260
136
We really should respect people's choices as long is does not affect the rest of us. In these communities it's a matter of etiquette, if not common sense.
I don't know if this is directed at me but I meant no disrespect. If I suddenly disappeared I would expect (hope) some of the people that I have been having in-depth discussions with for the past 20+ year might wonder what had happened to me. My post was one of respect and concern, not simple curiosity.
 

AMDK11

Senior member
Jul 15, 2019
348
246
116
I'm curious how Intel's "new" approach in LionCove will affect IPC's profit.

GoldenCove has 5x ALU, but it is 3x FP-ALU + 2x ALU. You can see from Zen4 how 4x ALU performs very well compared to GoldenCove, while having a separate scheduler and execution ports for the FPU.

LionCove has a separate schedule for 6x ALU and a separate schedule for 4 FPU ports.

Additionally, it has as many as 8 execution ports for memory operations, i.e. 6x AGU + 2x Store/Data (Zen5 4x AGU).
 
Last edited:

Hulk

Diamond Member
Oct 9, 1999
4,380
2,260
136
I'm curious how Intel's "new" approach in LionCove will affect IPC's profit.

GoldenCove has 5x ALU, but it is 3x FP-ALU + 2x ALU. You can see from Zen4 how 4x ALU performs very well compared to GoldenCove, while having a separate scheduler and execution ports for the FPU.

LionCove has a separate schedule for 6x ALU and a separate schedule for 4 FPU ports.

Additionally, it has as many as 8 execution ports for memory operations, i.e. 6x AGU + 2x Store/Data (Zen5 4x AGU).
Where did you get the Lion Cove architecture specifics? Is there a schematic out there somewhere?
 

AMDK11

Senior member
Jul 15, 2019
348
246
116
Where did you get the Lion Cove architecture specifics? Is there a schematic out there somewhere?
Yes. The diagram is hidden in the LunarLake core image.


LionCove P core:
8-Way Dispatch/Rename


a LionCove diagram can be compared to a RedwoodCove or GoldenCove diagram.

There seems to be a 4-Way predictor.

In the place of decoding and sending from the UOP cache, I counted 24-26(?) items. GoldenCove has 14, i.e. 6 from the decoder and 8 from the uop cache.

in total, LionCove has 18 execution ports compared to 12 of GoldenCove.

under the AGU+S/D units there are three blocks suggesting the division of L2 into 512KB + 2.5MB(?).

The L3 cache appears to be of a different design.


The Skymont core diagram shows 3x 3-Way decoding(Gracemont-Crestmont 2x 3-Way).

I'm sure Intel will present the same diagrams and descriptions at the LionCove and Skymont presentations.
 
Last edited:

S'renne

Member
Oct 30, 2022
136
99
61
Yes. The diagram is hidden in the LunarLake core image.


LionCove P core:
8-Way Dispatch/Rename


a LionCove diagram can be compared to a RedwoodCove or GoldenCove diagram.

There seems to be a 4-Way predictor.

In the place of decoding and sending from the UOP cache, I counted 24-26(?) items. GoldenCove has 14, i.e. 6 from the decoder and 8 from the uop cache.

in total, LionCove has 18 execution ports compared to 12 of GoldenCove.

under the AGU+S/D units there are three blocks suggesting the division of L2 into 512KB + 2.5MB(?).

The L3 cache appears to be of a different design.


The Skymont core diagram shows 3x 3-Way decoding.

I'm sure Intel will present the same diagrams and descriptions at the LionCove and Skymont presentations.
That's actually pretty interesting
 

AMDK11

Senior member
Jul 15, 2019
348
246
116
I quickly described the LionCove diagram, but it does not contain all the data, and the photo is not of high resolution, so you need to make sure by looking at the neighboring cores.
LionCove Core Diagram.png


Architecting%20Our%20Next%20Gen%20Power%20Efficient%20Processor_FINAL%20CLEAN-12.png
 
Last edited:

SiliconFly

Golden Member
Mar 10, 2023
1,234
641
96
Yes. The diagram is hidden in the LunarLake core image.

LionCove P core:
8-Way Dispatch/Rename

a LionCove diagram can be compared to a RedwoodCove or GoldenCove diagram.

There seems to be a 4-Way predictor.

In the place of decoding and sending from the UOP cache, I counted 24-26(?) items. GoldenCove has 14, i.e. 6 from the decoder and 8 from the uop cache.

in total, LionCove has 18 execution ports compared to 12 of GoldenCove.

under the AGU+S/D units there are three blocks suggesting the division of L2 into 512KB + 2.5MB(?).

The L3 cache appears to be of a different design.

The Skymont core diagram shows 3x 3-Way decoding(Gracemont-Crestmont 2x 3-Way).

I'm sure Intel will present the same diagrams and descriptions at the LionCove and Skymont presentations.
Excellent 👍
 

Saylick

Diamond Member
Sep 10, 2012
3,401
7,177
136
Inb4 WTFTech writes a new article on this.

If any of their authors is in these threads and sees this, you can go suck it!

Yes. The diagram is hidden in the LunarLake core image.


LionCove P core:
8-Way Dispatch/Rename


a LionCove diagram can be compared to a RedwoodCove or GoldenCove diagram.

There seems to be a 4-Way predictor.

In the place of decoding and sending from the UOP cache, I counted 24-26(?) items. GoldenCove has 14, i.e. 6 from the decoder and 8 from the uop cache.

in total, LionCove has 18 execution ports compared to 12 of GoldenCove.

under the AGU+S/D units there are three blocks suggesting the division of L2 into 512KB + 2.5MB(?).

The L3 cache appears to be of a different design.


The Skymont core diagram shows 3x 3-Way decoding(Gracemont-Crestmont 2x 3-Way).

I'm sure Intel will present the same diagrams and descriptions at the LionCove and Skymont presentations.
Looks like 8-way decode for LNC? On the Mop cache side, it looks like an additional 12?
1714341866677.png

1714341935296.png
 
Last edited:

AMDK11

Senior member
Jul 15, 2019
348
246
116
Inb4 WTFTech writes a new article on this.

If any of their authors is in these threads and sees this, you can go suck it!


Looks like 8-way decode for LNC? On the Mop cache side, it looks like an additional 12?
View attachment 98053

View attachment 98054
Note that Intel describes this part as a predictor in the diagram.

And the MSROM may have been moved higher next to L1-I to accommodate all the decoding and sending entries from the uop cache.

Intel-Architecture-Day-2021-Golden-Cove-Performance-Core-Overview.jpg
 
Last edited:

S'renne

Member
Oct 30, 2022
136
99
61
Lion cove is 8 wide like apple's firestorm core.. hope they get high ipc at low clocks too
Seems like the intention for Lion Cove onwards is following a similar path as Apple over AMD in core designs. Wasn't it Kepler or whoever it was suggesting that AMD has higher power draw and drastic performance improvement whereas Intel is finally going for sane power usage, maybe even lower with Lion Cove with performance uplift despite lower clocks?
 
  • Like
Reactions: Henry swagger

Joe NYC

Platinum Member
Jun 26, 2021
2,337
2,955
106
Seems like the intention for Lion Cove onwards is following a similar path as Apple over AMD in core designs. Wasn't it Kepler or whoever it was suggesting that AMD has higher power draw and drastic performance improvement whereas Intel is finally going for sane power usage, maybe even lower with Lion Cove with performance uplift despite lower clocks?

I think this is relative to the starting point (previous gen) not relative to competition.
 

Henry swagger

Senior member
Feb 9, 2022
450
284
106
Seems like the intention for Lion Cove onwards is following a similar path as Apple over AMD in core designs. Wasn't it Kepler or whoever it was suggesting that AMD has higher power draw and drastic performance improvement whereas Intel is finally going for sane power usage, maybe even lower with Lion Cove with performance uplift despite lower clocks?
Yeah.. apple really shows high clocks are useless if you have a good architecture.. apple is the gold standard in efficiency on laptop
 

H433x0n

Golden Member
Mar 15, 2023
1,090
1,305
96
This video will surely start an entertaining conversation.

Place your bets as to how fellow forum contributors will respond.. the options are listed below:

A) paid for shill review
B) Measurement error
C) Unfair comparison
D) All of the above
 
  • Like
Reactions: Henry swagger

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
25,782
14,815
136
This video will surely start an entertaining conversation.

Place your bets as to how fellow forum contributors will respond.. the options are listed below:

A) paid for shill review
B) Measurement error
C) Unfair comparison
D) All of the above
None of the above.... IMO, they both had places where they won, but overall it really was pretty even. Thats the part I disagree with the reviewer on. But I will agree that its a stopgap by both for next years Zen 5 vs Lunar lake that we should wait for.
 

gdansk

Platinum Member
Feb 8, 2011
2,499
3,401
136
This video will surely start an entertaining conversation.

Place your bets as to how fellow forum contributors will respond.. the options are listed below:

A) paid for shill review
B) Measurement error
C) Unfair comparison
D) All of the above
Here you go: in the real world it looks easier to configure Phoenix refresh than MTL (which so many vendors have messed up now).
 
  • Like
Reactions: lightmanek

Hitman928

Diamond Member
Apr 15, 2012
5,642
8,894
136
This video will surely start an entertaining conversation.

Place your bets as to how fellow forum contributors will respond.. the options are listed below:

A) paid for shill review
B) Measurement error
C) Unfair comparison
D) All of the above

Only thing I'll say about that review is their battery life test for "internet browsing" is ridiculous. I've commented on it before but it's probably the worst browsing test out there. Anyway, here are some additional reviews comparing both AMD and Intel models that show things in a bit different light. Make of it as you will.


 

Abwx

Lifer
Apr 2, 2011
11,181
3,893
136
Only thing I'll say about that review is their battery life test for "internet browsing" is ridiculous. I've commented on it before but it's probably the worst browsing test out there. Anyway, here are some additional reviews comparing both AMD and Intel models that show things in a bit different light. Make of it as you will.




In the Hardware Canucks fake review the AMD APU allegedly at 41W has 1h26 battery life at full load, while the MTL at allegedly 34W has 1h17, and that s with a same battery.
Obviously the MTL laptop use more power in the benches, Hardware Canucks are tricking the numbers.

Same for the higher temperature of PHX, they do no state the fan noise but it makes no doubt that it spin much harder in the MTL laptop, but since PHX has a higher temp they make people believe that it consume more, that s how you deceive the masses.
 

Geddagod

Golden Member
Dec 28, 2021
1,216
1,183
106
Only thing I'll say about that review is their battery life test for "internet browsing" is ridiculous. I've commented on it before but it's probably the worst browsing test out there. Anyway, here are some additional reviews comparing both AMD and Intel models that show things in a bit different light. Make of it as you will.


Similar battery life between MTL and PHX/HWK for these laptop models it looks like.
In the Hardware Canucks fake review the AMD APU allegedly at 41W has 1h26 battery life at full load, while the MTL at allegedly 34W has 1h17, and that s with a same battery.
Obviously the MTL laptop use more power in the benches, Hardware Canucks are tricking the numbers.

Same for the higher temperature of PHX, they do no state the fan noise but it makes no doubt that it spin much harder in the MTL laptop, but since PHX has a higher temp they make people believe that it consume more, that s how you deceive the masses.
Jeezus the cope is sad. Not everything is a conspiracy.