Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 294 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Tigerick

Senior member
Apr 1, 2022
686
574
106
PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Clockspeed.png
 

Attachments

  • PantherLake.png
    PantherLake.png
    283.5 KB · Views: 23,978
  • LNL.png
    LNL.png
    881.8 KB · Views: 25,450
Last edited:

Ghostsonplanets

Senior member
Mar 1, 2024
500
890
96
Which part of the system is LionCove because I can't recognize it?
View attachment 97425
left 4 Skymont, right 4 Lion Cove. Below Skymont is it's cache iirc and between the 4 Lion is their cache.
Also, bit of a guessing from Olrak:

GK3IUxmbkAAzu8N.jpeg


"ThunderShock":

Although it is just a rendering instead of the floorplan, it still has some questions on label.
The NPU site looks like the ME, and I think VPU/NPU should be close to the IMC, the above of ME.🤔


"If this is an accurate depiction of the floorplan, that would mean a Skymont cluster is now around 2 Lion Cove's worth of Area

I can see why people are hyping SKT as the best part of ARL. They seem to be heavily investing area into E-cores"
 
  • Like
Reactions: spursindonesia

Ghostsonplanets

Senior member
Mar 1, 2024
500
890
96
Core size numbers from here. Skymont grows big time unlike Lion Cove versus MTL on Intel 4.


Lunar Lake:
P core: 4.55mm²
E core cluster: 8,1mm²
E core (without L2): 1.52mm²

MTL:
P: 5,33mm²
E cluster: 5,9mm²
E core only: 1,04mm²

ADL:
P: 7,12mm²
E cluster: 8,3mm²
E core only: 1,59mm²
Intel must be taking a lot of advantage from TSMC N3 density and perhaps even some denser libraries instead of the usual UHP or HP libraries they use. I can't remember the last time an Intel Core was so small.

And Lion Cove is supposed to be an even wider and deeper core. Quite interesting.
 

AMDK11

Senior member
Jul 15, 2019
325
219
116
View attachment 97425
left 4 Skymont, right 4 Lion Cove. Below Skymont is it's cache iirc and between the 4 Lion is their cache.
The question now is whether the structure of Lion Cove matches the actual system. Is it just loose graphics without maintaining the correct structure with image confirmation?

LionCove has 2.5-3MB L2.

EDIT:
This is the same level of visualization as RedwoodCove in Meteorlake, which does not have much to do with the actual structures of the P core.
I'm still waiting for an actual photo of the LionCove core structure.
 
Last edited:

Gzxy

Junior Member
Apr 14, 2024
9
9
36
Intel must be taking a lot of advantage from TSMC N3 density and perhaps even some denser libraries instead of the usual UHP or HP libraries they use. I can't remember the last time an Intel Core was so small.

And Lion Cove is supposed to be an even wider and deeper core. Quite interesting.
P-cores dropped hyper threading. That thing takes lots of space.

P-cores are clocked probably a lot lower than previous gens for efficiency and thus they use as you said high density libs. I am not sure but i believe all previous gens U, H, HX P-cores where the same exactly and they just modified clocks and disabled parts of the cache. This is not the case since LNL is not meant for high TDPs.

 
  • Like
Reactions: Ghostsonplanets

Ghostsonplanets

Senior member
Mar 1, 2024
500
890
96
P-cores dropped hyper threading. That thing takes lots of space.
Oh! I wasn't aware HT was that much of an area eater
P-cores are clocked probably a lot lower than previous gens for efficiency and thus they use as you said high density libs
Xino shared that LNL EV-QS can reach 4.9GHz max turbo clock, so it isn’t that low clocked. Still, 4.9GHz would probably be feasibly with HD libs given how AMD was able to clock in the same range with Zen 2/Zen 3.
 

SiliconFly

Golden Member
Mar 10, 2023
1,127
576
96
If a "Skymont cluster is now around 2 Lion Cove's worth of Area", then I think the chances of us seeing ARL 8P+32E in pretty much non-existent!

Makes the die way too large and very expensive at the cost of serious yield issues. Looks grim.

So, there's this guy... they call him dimlid; they say he can predict the future...
 

Hulk

Diamond Member
Oct 9, 1999
4,353
2,216
136
Raptor Cove has about 45% or so better IPC than Gracemont when it comes to single core. So while the increased size of Skymont is enticing I find it hard to believe Skymont will approach Raptor Cove IPC, which would be needed for Arrow Lake to compete with Raptor Lake in MT.

Houston, we have a problem.
 

Saylick

Diamond Member
Sep 10, 2012
3,361
7,056
136
Oh! I wasn't aware HT was that much of an area eater
It shouldn’t be. Iirc, SMT only added like 10% more core area than without it. Additionally, we aren’t sure if LNC has SMT but it’s just turned off. I suspect it wasn’t designed from the ground up to be a pure non-SMT design, but the disabled SMT allows for easier validation, which means faster time-to-market, and less chance of security vulnerabilities.

Edit: spelling.
 
Last edited:

Hulk

Diamond Member
Oct 9, 1999
4,353
2,216
136
It shouldn’t be. Iirc, SMT only added like 10% more core area than without it. Additionally, we aren’t sure if LNC has SMT but it’s just turned off. I suspect it wasn’t designed from the ground up to be a pure non-SMT design, but the disabled SMT allows for easier validation, which means faster time-to-market, and less chance of security vultures.

Also while the lack of HT will diminish MT performance among the P cores, it will allow the P's to reach higher clocks with less power and heat when there are compute intensive threads thrown their way. Of course this assumes the E's are capable of handling all of the "lighter work" the missing logical cores would have been working on.
 
  • Like
Reactions: igor_kavinski

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
25,722
14,751
136
Also while the lack of HT will diminish MT performance among the P cores, it will allow the P's to reach higher clocks with less power and heat when there are compute intensive threads thrown their way. Of course this assumes the E's are capable of handling all of the "lighter work" the missing logical cores would have been working on.
I think the reason why Intel dropped HT was, that their implementation was far more susceptible to security holes than AMDs, and this was an easy way to eliminate that as well as higher clock speeds and a loss of only max 20% performance, and allowed the e-cores to make it up ??
 

Henry swagger

Senior member
Feb 9, 2022
418
264
106
Raptor Cove has about 45% or so better IPC than Gracemont when it comes to single core. So while the increased size of Skymont is enticing I find it hard to believe Skymont will approach Raptor Cove IPC, which would be needed for Arrow Lake to compete with Raptor Lake in MT.

Houston, we have a problem.
It will.. wait for benchmark leaks
 

coercitiv

Diamond Member
Jan 24, 2014
6,343
12,601
136
Also while the lack of HT will diminish MT performance among the P cores, it will allow the P's to reach higher clocks with less power and heat when there are compute intensive threads thrown their way.
Feels like we've been over this before, removing SMT is an efficiency loss, not a win. The catch is the loss will only exist in benchmarks, in most consumer workloads the number of threads available from the P+E combo will be high enough to out-scale the software. As for the area improvements, I would really wait and see for the benefits of removing SMT and AVX-512. There is a non-zero chance these features are just disabled in ARL.
 
  • Like
Reactions: Tlh97

ondma

Platinum Member
Mar 18, 2018
2,745
1,320
136
Feels like we've been over this before, removing SMT is an efficiency loss, not a win. The catch is the loss will only exist in benchmarks, in most consumer workloads the number of threads available from the P+E combo will be high enough to out-scale the software. As for the area improvements, I would really wait and see for the benefits of removing SMT and AVX-512. There is a non-zero chance these features are just disabled in ARL.
I have mentioned this before, but it makes one wonder how loss of HT will affect gaming. Without E cores, and with lower core counts, we saw a definite lack non HT cpus to handle higher gaming workloads (e.g. 2500k vs 2600K). Did HT help gaming with Raptor Lake, or do the E cores step in? Is eight strong P cores by themselves enough?
 

coercitiv

Diamond Member
Jan 24, 2014
6,343
12,601
136
I have mentioned this before, but it makes one wonder how loss of HT will affect gaming. Without E cores, and with lower core counts, we saw a definite lack non HT cpus to handle higher gaming workloads (e.g. 2500k vs 2600K). Did HT help gaming with Raptor Lake, or do the E cores step in? Is eight strong P cores by themselves enough?
With games we are still at a point where a strong 6-core is better than 8+ weaker cores. From 6 cores onward the memory subsystem matters more (cache, memory speed etc). Look at how close 14600K gets to 14700K, that's probably just the difference in L3 cache. We could also look at 7600X vs. 7700X, there we have influence from E cores and the L3 cache is identical.

6c.png

I would argue that 8C/8T will do fine in the next few years with the support of E cores and maybe some more APO style optimizations. Cache size, speed and overall latencies (memory, core-to-core etc) will matter a lot more than the presence of SMT.
 
Jul 27, 2020
17,505
11,286
106
I suspect it wasn’t designed from the ground up to be a pure non-SMT design, but the disabled SMT allows for easier validation, which means faster time-to-market, and less chance of security vulnerabilities.
I hope you are right. This could open the possibility of an SMT enablement firmware patch post launch, maybe months or even a year later.
 

Hulk

Diamond Member
Oct 9, 1999
4,353
2,216
136
Feels like we've been over this before, removing SMT is an efficiency loss, not a win. The catch is the loss will only exist in benchmarks, in most consumer workloads the number of threads available from the P+E combo will be high enough to out-scale the software. As for the area improvements, I would really wait and see for the benefits of removing SMT and AVX-512. There is a non-zero chance these features are just disabled in ARL.
While there is no doubt HT increases efficiency with a non-hybrid design, I'm not so sure about a hybrid design where we have cores specifically designed to handle ST (or low thread count) work loads and additional cores designed to handle high thread count workloads. We have a new paradigm with more variables to consider.
 

coercitiv

Diamond Member
Jan 24, 2014
6,343
12,601
136
While there is no doubt HT increases efficiency with a non-hybrid design, I'm not so sure about a hybrid design where we have cores specifically designed to handle ST (or low thread count) work loads and additional cores designed to handle high thread count workloads. We have a new paradigm with more variables to consider.
Adding another set of cores in the mix does not change the outcome, the work done by the P cores can still be optimized. Consider you run a highly parallelized workload on a 8P+16E / 24T CPU, so SMT is disabled. The task is split between the P and E cores based on predetermined ratios, and the work done by the 8P/8T cores is finite. That same work can be done more efficiently by 8P/16T with lower clocks and lower voltage, as long as there's good scaling from 8T to 16T. The work done by the E cores is already accounted for.

I think SMT is the victim of a misunderstanding based on the power race in the recent years. Yes, SMT will increase power and temps when allowed to push the package power higher. However, when enforcing a sane power limit, SMT increases efficiency instead.