Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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SiliconFly

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I wonder if some clever game engine developer (Epic?, makers of UE5) could masquerade useful and much needed data into the ADM cache as offscreen textures. Would be a lot of work and only useful if it gives a big boost and they expect the ADM to become a permanent fixture of future Intel mobile CPUs.
it's still not clear whether MTL's base tile is an active interposer with ADM or a separate stacked layer on top of a passive base tile. But either way, it's a expensive option and ADM will only appear on select models cos a passive base tile without any ADM is lot lot cheaper.

And since ADM is tied directly with the tGPU as L3, it'll significantly reduce bandwidth latency thereby increasing tGPU performance. The tGPU in a top-end SKU should be on par with a RTX 3050 at best. Not that it matters considering majority of the genpop don't care about GPU performance.
 

SiliconFly

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Hope you are right, but I wish I could share your optimism. Only time will tell, but that is a very ambitious cadence, not something Intel has pulled off successfully recently. I am troubled by the RL refresh too. It is too reminiscent of Skylake and all its refreshes and makes me wonder is they are on track.
Even Intel is troubled by RPL refresh too! :joycat:
 

H433x0n

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They're not only reaching parity but surpassing TSMC N3 in Q3 2024 with Intel 20A. Even though it sounds too good to be true, Intel 20A test chips have already been taped out and Intel Arrow Lake on 20A is well on track too with higher PPA than TSMC N3. It's gonna be a killer product with industry leading tech like gaafets & power vias. Something even TSMC won't have till 2026!!!!!! And thats no small feat!

Intel takes the lead next year both in CPUs & process nodes. Sadly, AMD & TSMC are taking the back seat starting Q3 2024.

A side note for AMD fanboys: Both Arrow Lake & Zen 5 are coming out in Q3 2024. And Zen 5 desktop & laptop cpus are based on the outdated tsmc 4nm node & Intel Arrow Lake cpus are based on the new cutting-edge Intel 2nm node. Arrow Lake is more than a node ahead of Zen 5! It's gonna be a bloodbath! Zen 5 will look like Rocket Lake when compared to Arrow Lake!
I can't tell if this is sarcasm but I agree on Intel reaching parity with TSMC is more likely than not. I would argue they're really only ~6 months TSMC on FinFet as of today, although their PDK is so far behind that FinFet in general is sort of a lost cause. They actually have sampled their 18A node to potential customers, so I'm not sure what that means in the grand scheme of things. Presumably it means there is enough of a PDK available to produce some sample wafers to determine performance characteristics.
 

Doug S

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Even if Intel can get 20A and 18A out on that aggressive schedule, what yields are they going to get? How many wpm can they run?

Samsung has been keeping pace or beating TSMC if you read their announcements, but their latest nodes are reportedly yielding terribly and they aren't producing that many so it doesn't count for much in the real world.

I'll believe Intel has turned the corner and taken the lead when there are credible rumors Apple is looking at having them make A19 in 2025 or something like that. If all they can do is push out certain high revenue SKUs of Intel CPUs but the bulk of their production remains on older nodes it will clear what is really going on.
 

SiliconFly

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I can't tell if this is sarcasm but I agree on Intel reaching parity with TSMC is more likely than not. I would argue they're really only ~6 months TSMC on FinFet as of today, although their PDK is so far behind that FinFet in general is sort of a lost cause. They actually have sampled their 18A node to potential customers, so I'm not sure what that means in the grand scheme of things. Presumably it means there is enough of a PDK available to produce some sample wafers to determine performance characteristics.
The generally overlooked fact is, Intel 4 & 20A are purpose-built slim nodes for very specific products. Compared to fat full-stack nodes like Intel 7, 18A, TSMC N3, N2, etc. Actually, these node comparisons may not even be reasonable because i feel we shouldn't even classify a slim node as a proper node. They're apples and oranges. For example, the amount of investment that goes in 20A pales in comparison to N2.

18A PDK 0.5 was released months back to IFS customers. Gives them a head start. But then again, TSMC has a large customer base (something Intel doesn't). So, when TSMC N2 makes a ton of money on release in 2026, Intel 18A may not... even though it's two years early with cutting edge tech like bpd & gaa. It's just business.

20A & 18A may not make a much money for Intel. But the products Intel make using 20A & 18A should definitely be cutting edge (assuming yields). And considering intel 4 & 20A are purpose-built with very specific HP libraries, the chances of them succeeding are pretty high too.

And IFS is just Intel trying to de-risk its fat nodes Intel 3 & 18A. And it takes many many years to succeed.
 
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SiliconFly

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Even if Intel can get 20A and 18A out on that aggressive schedule, what yields are they going to get? How many wpm can they run?

Samsung has been keeping pace or beating TSMC if you read their announcements, but their latest nodes are reportedly yielding terribly and they aren't producing that many so it doesn't count for much in the real world.

I'll believe Intel has turned the corner and taken the lead when there are credible rumors Apple is looking at having them make A19 in 2025 or something like that. If all they can do is push out certain high revenue SKUs of Intel CPUs but the bulk of their production remains on older nodes it will clear what is really going on.
IFS is many years away. My wild guess would be more than a decade at least. Intel needs a miracle to take on a IFS customer like Apple in 2025. I believe 2030 sounds more reasonable at best. Just my opinion.

Many actually miss this interesting fact. The biggest IFS customer for Intel is Intel itself. 20A & 18A may not make much money for Intel from foundry business, but if Intel manages to make good products with these and capture market share + make a decent profit, that should be good enough.
 
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H433x0n

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The generally overlooked fact is, Intel 4 & 20A are purpose-built slim nodes for very specific products. Compared to fat full-stack nodes like Intel 7, 18A, TSMC N3, N2, etc. Actually, these node comparisons may not even be reasonable because i feel we shouldn't even classify a slim node as a proper node. They're apples and oranges. For example, the amount of investment that goes in 20A pales in comparison to N2.

18A PDK 0.5 was released months back to IFS customers. Gives them a head start. But then again, TSMC has a large customer base (something Intel doesn't). So, when TSMC N2 makes a ton of money on release in 2026, Intel 18A may not... even though it's two years early with cutting edge tech like bpd & gaa. It's just business.

20A & 18A may not make a much money for Intel. But the products Intel make using 20A & 18A should definitely be cutting edge (assuming yields). And considering intel 4 & 20A are purpose-built with very specific HP libraries, the chances of them succeeding are pretty good too.

IFS is just Intel trying to de-risk its fat nodes Intel 3 & 18A. And it takes many many years to succeed.
I think they could pull off better volume than Samsung’s current business with the transition to GAAFET assuming they execute as planned. For example, I could see Nvidia dual sourcing some of their wafers.

TSMC isn’t a realistic target for the foreseeable future. Intel themselves proclaim their goal is to be the 2nd largest foundry by 2030, which I don’t think is an impossible goal. Their main issue is that they can’t be cost competitive and I don’t see how they’ll ever be able to compete on price against fabs in Taiwan and South Korea.
 

Exist50

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Intel 4 is in excellent shape according to both Intel and certain industry insiders. Some have claimed yields are even better than the Intel 7 variants.
Where have you seen that claim? I doubt yields are better than Intel 7 before they've even started proper volume production.
It really only comes down to catching up / surpassing TSMC. If they reach parity or surpass TSMC then the CPU performance/watt problem solves itself.
Intel still has big design issues they need to solve, especially around power efficiency and battery life. A competitive node helps, but isn't sufficient. Notice how their battery life figures actually got worse TGL->ADL. They have a lot of work to do on the core side for loaded perf/watt, and then on the SoC side for battery life.
(4) MTL memory latency is definitely not inferior to RPL.
I expect memory latency to be one of MTL's great weaknesses. AFAIK, one of their main architects in that area left the company midway through MTL. And that's even ignoring any die to die penalty.
Intel Arrow Lake on 20A is well on track too with higher PPA than TSMC N3
We'll see. Intel seems to view those nodes as pretty comparable, if they've mixing them across the product line.
 

H433x0n

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Intel still has big design issues they need to solve, especially around power efficiency and battery life. A competitive node helps, but isn't sufficient. Notice how their battery life figures actually got worse TGL->ADL. They have a lot of work to do on the core side for loaded perf/watt, and then on the SoC side for battery life.

We'll see. Intel seems to view those nodes as pretty comparable, if they've mixing them across the product line.
I still think you’re underestimating the effect the node has on perf/watt. The same core (Raptor Cove vs Golden Cove) had a 15% perf/watt jump on mobile products by just moving to Intel 7 Ultra.

You really don’t think MTL isn’t going to outperform Phoenix on perf/watt? How far ahead do you believe Phoenix is right now with respect to battery life?

Edit: There is no public literature on 18A as far as I know. Based off of what we know about Intel 4, for Intel 18A to be comparable to N3P, it’d have to have the same performance characteristics as Intel 3.
 
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Exist50

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I still think you’re underestimating the effect the node has on perf/watt. The same core (Raptor Cove vs Golden Cove) had a 15% perf/watt jump on mobile products by just moving to Intel 7 Ultra.
Raptor Lake wasn't just process improvements. And generally speaking, process improvements can get you double digit percent changes. Very significant, sure, but not enough
You really don’t think MTL isn’t going to outperform Phoenix on perf/watt? How far ahead do you believe Phoenix is right now with respect to battery life?
At least under load, I expect Phoenix to beat out Meteor Lake in perf/watt. To what degree, I'm not going to guess. Battery life might be more interesting, as that's much more about SoC-level power management. Historically, that has been an advantage for Intel vs AMD, and a horrible disadvantage vs Apple and Qualcomm. However, AMD's been making huge improvements there, so tbd.
Edit: There is no public literature on 18A as far as I know. Based off of what we know about Intel 4, for Intel 18A to be comparable to N3P, it’d have to have the same performance characteristics as Intel 3.
Intel 4/3 should be more like TSMC N5/N4 class competitors. There's a reason Intel's using N3 for Arrow Lake and Lunar Lake instead of Intel 3.
 
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H433x0n

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Intel 4/3 should be more like TSMC N5/N4 class competitors. There's a reason Intel's using N3 for Arrow Lake and Lunar Lake instead of Intel 3.
I'm guessing you're assuming that it's going to be heavily scaled back? The logic density is closer to N3 than it is to N4, while memory density is ~14% behind N4. Unless the half node step from Intel 4 -> 3 gets completely botched, the Intel 3 node will have the best performing HP cells available.

I've honestly got no clue why they're using N3, assuming that is what they're actually doing. N3x won't even be available for their launch window, which was the original node they were rumored to use.
 

JoeRambo

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I expect memory latency to be one of MTL's great weaknesses. AFAIK, one of their main architects in that area left the company midway through MTL. And that's even ignoring any die to die penalty.

This requires a deeper discussion. Nowadays things have moved beyond just memory latency and i prefer term "memory subsystem". So things like larger L2 shielding weak L3, L3 cache size, X3D caches and L4 caching schemes are all accommodated into "average" memory latency that core has during certain workload.

So going from lower levels:

1) L2 to remain 2MB, this is a strong point of their memory subsystem and a lot of requests that spill from L2 on Z4, stay near core and save power and improve performance.
2) L3 => ADL had disaster level of L3, RPL mostly fixed it. I find it hard to imagine* that Intel managed to degrade L3 cache in compute die. That would make little sense to me. In fact their clock target rumours, the fact that IO is no longer on die and there are less nodes on intereconnect inside compute dies might mean:
L3 slice clock is now synchronous with cores and that improves both bandwidth and latency big time. AMD has excellent L3 for 8C CCD and there is no reason why Intel cannot have even better one.

So 1-2 are huge positives and would improve performance and power efficiency quite some. There can be L3 latency improvement of some 5-8ns.

3) This is gonna be Intel's ZEN2 like multi chip so i would not expect it to have good performance. "Infinity fabric" type of problems with clocking, latency and bandwidth are practically a certainty.

I think 2 and 3 have a chance to completely cancel out latency penalties, Intels current L3 is that bad even in RPL incarnation.

4) So now we have reached SoC tile where IMC and L4 cache resides. Without L4 cache enabled i think the chip could have similar memory subsystem performance to RPL, esp if DDR5 speed support is increased and IMC team does better than average.

It's with L4 enabled that things get hazy. checking tags for 512MB of L4 is not free operation and would add a quite some latency to each miss that has to go to memory. That's where I expect memory miss latency to degrade in "absolute" ns terms.
Except obviously having 128-512MB of L4 would have "scaling" benefits for a lot of workloads.

One thing to consider about L4 cache -> 64MB of EDRAM in Broadwell era required ~ 2MB L3 used for tags.
We have another vendor throwing silicon in chunks of 64MB of L3 that clocks 5Ghz in X3D chips.
Therefore SRAM for checking tags is not that big of a problem anymore. Beancounter problem, not technical "if we use silicon for L4 tags we will destroy our L3 transistor budget" problem.


* i also had trouble imagining that there are idiots that can design L3 that has DDR4 level of latency, but it was "achieved" by Intel this year in server chip.
 
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mikk

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Intel(R) Core(TM) Ultra 7 1003H (family: 0x6, model: 0xaa, stepping: 0x4)
Detected 3400.000 MHz processor

Big clock speed improvements over the steppings. This is base clock speed right?

stepping 0x1 1200 Mhz .......probably ES1
stepping 0x2 2300 Mhz .......probably ES2
stepping 0x4 3200 Mhz .......probably QS (no generic CPU ID for the first time should be QS!)
 
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Hulk

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I still hold the opinion that there will be no MTL-S because of the tremendous scaling/refinement of the 10nm process and the ADL/RPL design. Raptor Lake set the bar very high in terms of clocks for the first crack at the next process tech to reach. Once Intel realized that they could refine/push this process even further with a Raptor Lake Refresh, coupled with the relatively minor IPC increase of MTL that was the end for MTL-S.

In addition, they can keep cranking out 10nm (Intel 7) with the fabs that are already set up for it while working out the kinks in Intel 4 with the limited supplies required for a MTL mobile release. Couple this with the fact that MTL is a test bed of sorts for the new tiled layout and is supposedly pushing iGPU to new heights and it makes perfect sense to focus on those aspects of this new design/process. Once this is all worked out the transition to Intel 4 and tiles across the board will commence. This is the safe play in case something goes terribly wrong with Intel 4 and/or MTL Intel still has a viable product to ship. It would be a huge gamble to put everything on the table for Intel 4 and "roll the dice" that is works. It's just not how Intel operates. Slow and steady is more their style.
 

coercitiv

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I still hold the opinion that there will be no MTL-S because of the tremendous scaling/refinement of the 10nm process and the ADL/RPL design.
I disagree. MTL was supposed to be used in the value segment, where max turbo clocks hit ~5GHz this generation. Whether it was a better fit than ARL-S is another story, but we do know the value segment is more sensitive to pricing and efficiency. To me, giving up on MTL-S seems to be about reevaluated production costs and/or volumes.
 
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Hulk

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I disagree. MTL was supposed to be used in the value segment, where max turbo clocks hit ~5GHz this generation. Whether it was a better fit than ARL-S is another story, but we do know the value segment is more sensitive to pricing and efficiency. To me, giving up on MTL-S seems to be about reevaluated production costs and/or volumes.
Yes that is a good insight, but production costs and volumes are directly related to not only the performance of the product in question but also other products in the manufacturers stack that can perform as well at lower manufacturing cost. Of course we each have our own opinions on this and this is a multivariate issue but I gleen from what we do know that one significant factor is the existence of another less production "risky" product as or more performant and less costly to produce, that being Raptor Refresh. Had it not existed or had Raptor not been as performant as it is would may have meant MTL-S would have see the light of day.
 

dullard

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Wow, Meteor Lake gets 40% frequency improvement at iso-power (c.f. i7-13700H/6P8E/2.4GHz/45W) .
Intel 4 is a great work...
I think you are making a few too many unexplained assumptions in that post.
1) The leak is for MTL-P with a 1003H name. You compared it to an RPL-H mobile part. Why did you not compare it to an RPL-P part?
2) As far as I can see, the leak didn't specify power used. You just assumed 45W. Or did I miss something?
3) I don't have experience reading the intel-gfx-ci.01.org data, but how do we know the 3.4 GHz processor is the P cores at base?

Intel was predicting a 20% improvement, so 40% would be quite a big deal. I'm just not sure that we can get to that conclusion with this data.
 
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mikk

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I think you are making a few too many unexplained assumptions in that post.
1) The leak is for MTL-P with a 1003H name. You compared it to an RPL-H mobile part. Why did you not compare it to an RPL-P part?


It's more likely a 45W SKU. We have seen Sisoft entries from MTL-P 45W which matches the older Ultra 5 1003H leak (same driver version). In this case it seems plausible Ultra 7 1003H is also a 45W SKU.


Intel was predicting a 20% improvement, so 40% would be quite a big deal. I'm just not sure that we can get to that conclusion with this data.

According to Raichu the efficiency target for MTL over Raptor Lake at the same performance is at 1.5x. MLID says 30-45% less energy than Raptor Lake-R at same performance below 45W. Efficiency gains don't come from a node improvement only if it's a new architecture. As for Meteor Lake they can gain a lot from a separate voltage rail for the E-cores and maybe DLVR is working (might work in RPL-R already).
 

eek2121

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IFS is many years away. My wild guess would be more than a decade at least. Intel needs a miracle to take on a IFS customer like Apple in 2025. I believe 2030 sounds more reasonable at best. Just my opinion.

Many actually miss this interesting fact. The biggest IFS customer for Intel is Intel itself. 20A & 18A may not make much money for Intel from foundry business, but if Intel manages to make good products with these and capture market share + make a decent profit, that should be good enough.
IFS has customers currently. Low volume specialty chips.
Where have you seen that claim? I doubt yields are better than Intel 7 before they've even started proper volume production.

Intel still has big design issues they need to solve, especially around power efficiency and battery life. A competitive node helps, but isn't sufficient. Notice how their battery life figures actually got worse TGL->ADL. They have a lot of work to do on the core side for loaded perf/watt, and then on the SoC side for battery life.

I expect memory latency to be one of MTL's great weaknesses. AFAIK, one of their main architects in that area left the company midway through MTL. And that's even ignoring any die to die penalty.

We'll see. Intel seems to view those nodes as pretty comparable, if they've mixing them across the product line.
Insiders that shall not be named.

A simple shrink from Intel 7 to Intel 4 would allow Raptor Lake to become more efficient than Zen 4. Keep that in mind.

EDIT: Raptor Lake on Intel 4 would need only 125W for the performance level that 230W allows for now.
 
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