Intel lists five challenges for IC scaling

[Idontcare]

Intel lists five challenges for IC scaling

At the International Solid-State Circuits Conference (ISSCC) here, Mark Bohr, Intel senior fellow and director of process architecture and integration at Intel Corp. (Santa Clara, Calif.), outlined the challenges and potential solutions. Bohr listed five major stumbling blocks--or challenges--for the 32-nm node and beyond:

http://www.eetimes.com/news/se...cleID=213402033&pgno=1

The first page (first 3 of 5 challenges) are an interesting read. The second page with the remaining two challenges not so much.

As always with the Intel guys, you got to read between the lines, and then take those between the lines readings and read between those lines, and repeat about five times before you can unravel what they are saying about their future process tech.

(take EUV, did he just say it won't be ready for 16nm? Or did he say 16nm won't be ready until EUV is ready, whenever that turns out to be...)

 

[soccerballtux]

Originally posted by: Idontcare

Intel lists five challenges for IC scaling

At the International Solid-State Circuits Conference (ISSCC) here, Mark Bohr, Intel senior fellow and director of process architecture and integration at Intel Corp. (Santa Clara, Calif.), outlined the challenges and potential solutions. Bohr listed five major stumbling blocks--or challenges--for the 32-nm node and beyond:

http://www.eetimes.com/news/se...cleID=213402033&pgno=1

The first page (first 3 of 5 challenges) are an interesting read. The second page with the remaining two challenges not so much.

As always with the Intel guys, you got to read between the lines, and then take those between the lines readings and read between those lines, and repeat about five times before you can unravel what they are saying about their future process tech.

(take EUV, did he just say it won't be ready for 16nm? Or did he say 16nm won't be ready until EUV is ready, whenever that turns out to be...)

22nm is the smallest node we can make with current immersion lithography processes. Need a higher frequency wave to etch traces beyond that. IIRC. The article seems to think 16nm is possible; all I've heard says otherwise.

 

[TuxDave]

Originally posted by: Idontcare

The first page (first 3 of 5 challenges) are an interesting read. The second page with the remaining two challenges not so much.

1) Crappier layout rules
2) Crappier device layout rules
3) Crappier wires

Nothing new here...

 

[pm]

Need a higher frequency wave to etch traces beyond that.

Or a lens, photoresist and/or immersion fluid that have a refractive index that are higher than those used now.

Still, it's clear that things are getting worse quickly - at least according to ITRS.

ITRS is predicting:
32nm 2009
22nm 2011
16nm 2018
11nm 2022

 

[Idontcare]

Originally posted by: TuxDave

Originally posted by: Idontcare

The first page (first 3 of 5 challenges) are an interesting read. The second page with the remaining two challenges not so much.

1) Crappier layout rules
2) Crappier device layout rules
3) Crappier wires

Nothing new here...

You layout guys all sound like the same broken record :laugh:

Oh and (3) would be crappier layout rules too.

We'll go to requiring you to use more and more redundant via drops to reduce IR loss as we make you run signals on both M1 and M2 in parallel (identical layout for M2 as M1).

When it comes to advances in the BEOL and new layout rules, everyone loses.

Originally posted by: pm

Need a higher frequency wave to etch traces beyond that.

Or a lens, photoresist and/or immersion fluid that have a refractive index that are higher than those used now.

Still, it's clear that things are getting worse quickly - at least according to ITRS.

ITRS is predicting:
32nm 2009
22nm 2011
16nm 2018
11nm 2022

Yeah the node cadence has got to slow down...says everyone who is competing with Intel :laugh:

I've no doubt you know this, but many posters here won't - the ITRS is a collection of committees staffed by essentially volunteers (albeit vetted and qualified) from the industry and essentially represents the moving average target of what the industry players in general want to see the industry head towards...it is no surprise that 5 out of 6 guys in the room all want to see 16nm pushed out to 2018 (or later), the one lone Intel committee member on that one is probably shaking their head thinking "do what you want guys, we'll see your 22nm in the marketspace with our 16nm in 2013".

 

[TuxDave]

Originally posted by: Idontcare

Originally posted by: TuxDave

Originally posted by: Idontcare

The first page (first 3 of 5 challenges) are an interesting read. The second page with the remaining two challenges not so much.

1) Crappier layout rules
2) Crappier device layout rules
3) Crappier wires

Nothing new here...

You layout guys all sound like the same broken record :laugh:

Oh and (3) would be crappier layout rules too.

We'll go to requiring you to use more and more redundant via drops to reduce IR loss as we make you run signals on both M1 and M2 in parallel (identical layout for M2 as M1).

When it comes to advances in the BEOL and new layout rules, everyone loses.

Not exactly a layout guy but more of a designer who's required to keep the layout guys happy.

But yeah routing redundant wires and vias have actually been done a ton even with today's technology. Imagine 8-10 Metal1 Vias hooking up two parallel M2 routes hooking up to 2 parallel M3 routes to a REALLY fat M4 route etc... fun times but it works.

 

[Idontcare]

Originally posted by: TuxDave
Not exactly a layout guy but more of a designer who's required to keep the layout guys happy.

But yeah routing redundant wires and vias have actually been done a ton even with today's technology. Imagine 8-10 Metal1 Vias hooking up two parallel M2 routes hooking up to 2 parallel M3 routes to a REALLY fat M4 route etc... fun times but it works.

Come on, less bitching, more Sandy Bridge. Stat!

Seriously though if you keep a running list of folks who absolutely hold no envy over your job then please by all means add me to it.

At 65nm and 45nm we really made some craptastic design rule requirements all for the sake of not wanting to bother to invest in the R&D expenditure to run a few more test splits with potential barrier/seed thickness improvements. Seeing how frivolous our process development management was with the layout guy's time and labor as they were forced to accommodate our design rule limits forever convinced me to never head into that occupation :laugh:

Then again it was the death knell of TI's process development trajectory...so maybe we were the outlier and you guys at Intel just have fat cushy jobs as you push around the process development guys. "I said metal fill density would be allowed to go as low as 1% you lacky's! now go make your CMP work with that and stop whining about topology"

 

[TuxDave]

Originally posted by: Idontcare

Originally posted by: TuxDave
Not exactly a layout guy but more of a designer who's required to keep the layout guys happy.

But yeah routing redundant wires and vias have actually been done a ton even with today's technology. Imagine 8-10 Metal1 Vias hooking up two parallel M2 routes hooking up to 2 parallel M3 routes to a REALLY fat M4 route etc... fun times but it works.

Come on, less bitching, more Sandy Bridge. Stat!

Seriously though if you keep a running list of folks who absolutely hold no envy over your job then please by all means add me to it.

At 65nm and 45nm we really made some craptastic design rule requirements all for the sake of not wanting to bother to invest in the R&D expenditure to run a few more test splits with potential barrier/seed thickness improvements. Seeing how frivolous our process development management was with the layout guy's time and labor as they were forced to accommodate our design rule limits forever convinced me to never head into that occupation :laugh:

Then again it was the death knell of TI's process development trajectory...so maybe we were the outlier and you guys at Intel just have fat cushy jobs as you push around the process development guys. "I said metal fill density would be allowed to go as low as 1% you lacky's! now go make your CMP work with that and stop whining about topology"

Surprisingly, working with the process development guys is a nice push/pull relationship. We tell them what we want lots of good wires and lots of metal layers, they tell us it'll increase the costs of fabrication and to keep dreaming. We end up having to change our arguments from "it'll enable some new feature and help us meet frequency targets" to "it'll let us shrink the die".