Intel Itanium 2 "Montecito" specs and versions

[IntelUser2000]

Current Itanium 2 processors running at 1.5GHz, with 6MB L3 has 32-bit x86 performance of similar clocked(1.5GHz) Xeon MP.

Next generation Itanium is on Intel's 90nm process and is code named "Montecito".

-90nm technology
-596mm2 die
-Dual core, per core it features
32KB L1 cache
1MB Instruction, 256KB Data L2 cache
12MB L3 cache
Offers same cache latency as previous Itaniums
Has same pipeline stages as previous Itaniums(8)
-Arbitration bus logic, think of Athlon X2's SRQ interface


9000 Sequence: Itanium²

Itanium² 9055: Montecino 1.8(2.0) Ghz/24M L3
Itanium² 9040: Montecino 1.6(1.8) Ghz/18M L3 *
Itanium² 9030: Montecino 1.7(1.8) Ghz/8M L3 *
Itanium² 9020: Montecino 1.4(1.6) Ghz/12M L3 *
Itanium² 9018: Montecino LV 1.2(1.4) Ghz/12M L3
Itanium² 9010: Montecino 1.6(1.8) Ghz/6M L3 *
* Proc Number +1 for FSB667 instead of 400/533

Power consumption figures:

1.30V 2.2GHz 110W
1.25V 2.1GHz 104W
1.20V 2.1GHz 95W
1.15V 1.9GHz 77W
1.10V 1.9GHz 71W
1.05V 1.8GHz 63W
1.00V 1.7GHz 57W
0.80V 1.2GHz 24W

Single FSB 667MHz has bandwidth of 10.8GB/s, there will be Dual FSB versions.

These are possible figures based on the schmoo plot of Montecito. Seeing as there is 1.2GHz LV version of Montecito, we might as well see 35W versions or lower.

Montecito's power management system allows the processor to NEVER exceed the set limit, which means the above figures are essentially same as max power.

According to some people's estimations, SPEC CPU2000 scores for single thread will be around ~1200/1200 with IA-32EL, which is equal to 3.06GHz Xeon with 1MB L3 cache and 533MHz FSB.

 

[Vegitto]

Originally posted by: IntelUser2000
Current Itanium 2 processors running at 1.5GHz, with 6MB L3 has 32-bit x86 performance of similar clocked(1.5GHz) Xeon MP.

Next generation Itanium is on Intel's 90nm process and is code named "Montecito".

-90nm technology
-596mm2 die
-Dual core, per core it features
32KB L1 cache
1MB Instruction, 256KB Data L2 cache
12MB L3 cache
Offers same cache latency as previous Itaniums
Has same pipeline stages as previous Itaniums(8)
-Arbitration bus logic, think of Athlon X2's SRQ interface


9000 Sequence: Itanium²

Itanium² 9055: Montecino 1.8(2.0) Ghz/24M L3
Itanium² 9040: Montecino 1.6(1.8) Ghz/18M L3 *
Itanium² 9030: Montecino 1.7(1.8) Ghz/8M L3 *
Itanium² 9020: Montecino 1.4(1.6) Ghz/12M L3 *
Itanium² 9018: Montecino LV 1.2(1.4) Ghz/12M L3
Itanium² 9010: Montecino 1.6(1.8) Ghz/6M L3 *
* Proc Number +1 for FSB667 instead of 400/533

Power consumption figures:

1.30V 2.2GHz 110W
1.25V 2.1GHz 104W
1.20V 2.1GHz 95W
1.15V 1.9GHz 77W
1.10V 1.9GHz 71W
1.05V 1.8GHz 63W
1.00V 1.7GHz 57W
0.80V 1.2GHz 24W

Single FSB 667MHz has bandwidth of 10.8GB/s, there will be Dual FSB versions.

These are possible figures based on the schmoo plot of Montecito. Seeing as there is 1.2GHz LV version of Montecito, we might as well see 35W versions or lower.

Montecito's power management system allows the processor to NEVER exceed the set limit, which means the above figures are essentially same as max power.

According to some people's estimations, SPEC CPU2000 scores for single thread will be around ~1200/1200 with IA-32EL, which is equal to 3.06GHz Xeon with 1MB L3 cache and 533MHz FSB.

I sure hope that's a typo, cause that die would be HUGE!

 

[jones377]

I sure hope that's a typo, cause that die would be HUGE!

It is not a typo, it's the actual size they have reported. In fact it's close to the limit to how big you can make a single die on a wafer.

BTW, I thought it had become cleared earlier than the 3x bandwidth of Montecito compared with 400MHz FSB Madison as reported earlier referred to the system level and not the Socket itself. This will be implemented through a dual FSB on the chipsets simular to how IBM has already done this for their latest Xeon chipset. Thus a 4-core Montecito system will have >3x (21.6GB/s vs 6.4GB/s) the bandwidth of a 4-core Madison system for example.

 

[IntelUser2000]

Yeah, Montecito will have 400/533/667MHz FSB versions. Apparently the 667FSB versions will have dual FSB, so more than 3x the bandwidth of the original Itanium 2's.

For the die size, the successor to it is supposed to have bigger cache(32MB?) at the same 90nm process, which I see it going to +700mm2 die size, if the rumors are true. Don't know if the bigger cache is true since it was supposed to be at 65nm.

Possible improvements:
IA32-EL software may have x86-64 support.
Better Multithreading capability

 

[ryanv12]

Can I fit it in my socket 939 board?