Intel Edison computer - based on Quark arch

[VirtualLarry]

http://www.xbitlabs.com/news/mobile...on_PC_in_Secure_Digital_Card_Form_Factor.html

 

[RU482]

The small compute package brings connectivity with Wi-Fi and Bluetooth LE, and has LPDDR2 and NAND flash storage as well as a wide array of flexible and expandable I/O capabilities.

Hmm, any specs on this device? Smells a bit like BS, but I'd love to be wrong

 

[crashtech]

Looks real:

http://www.intel.com/content/www/us/en/do-it-yourself/edison.html

 

[Broheim]

between this and the Galileo board it seems like intel is pretty serious about getting a dominant position in IoT.

 

[NTMBK]

Yay, a 486!

 

[VirtualLarry]

Yay, a 486!

At 400Mhz, no less! Should be much faster than a "classic" 486. I would be curious if it could run Windows 3.1.

 

[podspi]

At 400Mhz, no less! Should be much faster than a "classic" 486. I would be curious if it could run Windows 3.1.

It's also dual-core :biggrin:.

How power efficient are these? Are these going any lower than ARM currently is?

 

[Dresdenboy]

How power efficient are these? Are these going any lower than ARM currently is?

This is not comparable, since there are also very small and extreme LP ARM cores like the Cortex-M series. In a 40G process it uses 8µW/MHz dynamic power, so about 3.2mW at 400MHz. Area is 0.04 sqmm per core.
More here: http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php under "Specifications".

Back in the days of 386 and 486, ARM2 and ARM3 were very efficient desktop PC processors. But the Acorn computers using them were niche products (well, not in the UK).

 

[Nothingness]

As CPU are targetting lower sizes and lower perf the Intel CISC disadvantages strike back: the more complex decoders start taking a non negligible amount of area and power of the CPU.

OTOH this is a SoC with many features beyond the CPU, so it's likely the difference will be small and compensated by Intel process advantage.

The question is can Intel price this correctly?

 

[StrangerGuy]

As CPU are targetting lower sizes and lower perf the Intel CISC disadvantages strike back: the more complex decoders start taking a non negligible amount of area and power of the CPU.

OTOH this is a SoC with many features beyond the CPU, so it's likely the difference will be small and compensated by Intel process advantage.

The question is can Intel price this correctly?

Need this for my toaster, my bread would toast faster if the chip inside was 1000x faster.

 

[witeken]

As CPU are targetting lower sizes and lower perf the Intel CISC disadvantages strike back: the more complex decoders start taking a non negligible amount of area and power of the CPU.

Is this a CISC disadvantage? Isn't it a disadvantage of decoding from CISC to RISC?

The question is can Intel price this correctly?

Yes.

 

[podspi]

Need this for my toaster, my bread would toast faster if the chip inside was 1000x faster.

No, it won't :biggrin:

But who cares how fast the toast... toasts ... when your toaster will start toasting when you get out of the shower in the morning.

Think tasker in real life man.

 

[Nothingness]

Is this a CISC disadvantage? Isn't it a disadvantage of decoding from CISC to RISC?

What are you talking about?

 

[William Gaatjes]

Yay, a 486!

According to this article it is pentium based.
And an interesting mix. x86core with ARM AMBA BUS interconnect.

http://www.eetimes.com/document.asp?doc_id=1319726

10/7/2013 10:35 AM EDT

Quark, Intel's new Pentium-based architecture, is aimed head on at ARM in applications such as the Internet of the Things (IoT). But the fact that it uses ARM's AMBA bus interconnect underscores the vital importance of the ecosystem. It runs alongside a legacy serial bus to blocks such as the GPIO and real-time clock, separate from PCI Express and other serial interfaces.

The first instantiation of the core is used in the X1000 SoC. The specification, which was released at the end of last week, raises more questions than it answers for the SoC business, especially when you bring the IoT into the equation.

The way Intel has addressed the software ecosystem, with ports of Linux and VxWorks from Intel-owned Wind River and security from Intel-owned McAfee, highlights part of the challenge. Some SoC designers will welcome a ready-made software ecosystem, but this is primarily for Intel's customers buying the chip, rather than the core. Intel has said it will be a good long while before the IP is available on TSMC's technology.

Even then, there are key questions: How does this work as a multi-core device, both in homogeneous and heterogeneous systems? Exactly how the interfaces to graphics and security co-processors that need to be tightly coupled will work is not clear. Having a synthesizable core helps with this. But creating an effective, multi-core IP solution for third-party SoC designers could take a signiifcant amount of work, and both ARM and Imagination Technologies are well ahead. Of course, a multi-core-enabled device (perhaps the X2000), could be in the roadmap.

Another issue is where this new architecture will actually compete. SoCs based on ARM's M0+ Flycatcher core will not run Linux, although they do hit the sub-50-cent price point for the IoT, including security engines and targeted peripherals. With cache, wait states, legacy bus, and a larger area, Quark is unlikely to compete on area, price, and power. And with such price pressure, coupled with the memory and power issues, these are not going to be on the leading-edge 20nm and 14nm processes.

Atom is firmly aimed at the IoT gateway devices, and if Quark cannot get down to the silicon dust price point, it's not going to make a significant dent in the IoT market.

It seems Intel has a few large customers, including itself, lined up for Quark for wearable devices. But as exciting as it is to have a new architecture in the embedded SoC market, the opportunities for the wider market appear to be quite limited. A smartwatch running Linux (which should really mean WindRiver Android) is interesting, but are we likely to take the hit of Android for a sensor controller in the IoT? That's unlikely, since the space between the ultra-low-cost sensor/controller and gateway is not really clear, while a heterogeneous multicore version will play well in low-cost smartphones and smart devices, alongside Intel's wireless IP.

This first part is an exploratory device with lots of options. The dedicated, optimized SoCs will come when Intel actually gets to focus on its end applications.

 

[Nothingness]

According to this article it is pentium based.

It is an i486 micro-architecture (about half IPC of Pentium) with non-MMX Pentium instructions added.

 

[Shivansps]

Imagine 2 ASM1061 and port muiltipliers on a quark.



What i do not like is the number of gpios, seems way limited me.

 

[crashtech]

I think the idea is that this is kinda like a test case to see what developers will do with it, and feedback from that will drive refinements, possibly resulting in a number of variants tailored to different usage scenarios.

 

[William Gaatjes]

It is an i486 micro-architecture (about half IPC of Pentium) with non-MMX Pentium instructions added.

Yeagh.


A 486dX is according to wiki rated at 54mips @66MHz.
I wonder if there is really a market for this chip.
Intel is really using their fab muscles, 22nm and 400MHz...

 

[Shivansps]

Its a microcontroller, there is always market for these. Its wrong for people to compare it to R-PI for example.

I think what they need to do with it is actually sell that small "SD format" board, with pinouts, i whould more than interested to get some for a few proyects.

 

[William Gaatjes]

Its a microcontroller, there is always market for these. Its wrong for people to compare it to R-PI for example.

I think what they need to do with it is actually sell that small "SD format" board, with pinouts, i whould more than interested to get some for a few proyects.

You have a point. .
The development eco system , a high quality IDE with good support, short time to market is what is important to sell products like these.