Discussion Intel current and future Lakes & Rapids thread

[Geddagod]

YukkiAnns said these were older documents.
These should be somewhat apparent in the way Intel 4 is still described as Intel 7nm. GNR documents look a bit old, but not as old that GNR was just 2 compute tiles on Intel 4 and 96 cores?
Sierra Forest however gets the new node names- Intel 7 and Intel 3.
A little disappointed we don't get core counts for Sierra Forest haha.
Also where Sierra Forest AP?

 

[Geddagod]

Intel looks to be expecting around ~40 cores from each GNR tile.
SPR/EMR and GNR SP both have 350W TDP no?
~40% better aggregate performance. Nice.
80/64 = 25%, the remaining ~10% performance looks to be coming from better clocks+IPC. Impressive, considering GNR SP still has more cores and yet clocks better as well compared to EMR.
RWC IPC gains should be very low, I'm guessing most of the gains come from clocks.
In comparison, going from 84 cores vs 64 cores on the same node looks to be a ~10% loss in clocks (for Genoa and similar TDP). Same with going from 60 cores vs 48 cores for SPR (25% gain in cores just like 80/64 cores of GNR-AP vs EMR).
So the gain in frequency/watt from RWC is ~20%?
Hmmm sounds like that slide from Adored TV

 

[Geddagod]

But wait! Where is RWC+ Gelsinger promised us?
Looks like RWC+ isn't showing up, or is either such a minor update that it's not significant.
The bottom of the slides say 2021. 2024 is 3 years away. Idk if that's enough time to change the plan... for consumer products the timeline is 3 years, for server it has to be longer. But to add a new core, especially if it's similar and not a major change, it might not require the full 3 years of redevelopment, for example RPL only took 2 and a half years not 3.

 

[IntelUser2000]

But wait! Where is RWC+ Gelsinger promised us?
Looks like RWC+ isn't showing up, or is either such a minor update that it's not significant.

Those slides are old enough that it's pre-change. It was based on Intel 4 and then it got changed to Intel 3+RWC with 10% extra gain. They can't change back to plain-vanilla RWC unless they moved it back to Intel 4.

The very interesting thing is, 80C for SP and 120C for AP is what MLID said. This must be the slide he was referring to?

 

[Exist50]

Looks like RWC+ isn't showing up, or is either such a minor update that it's not significant.

Probably. Seems to basically just be RWC on Intel 3. Maybe they'll make a few tweaks, but if they didn't even bother to give it a new name like they did Raptor Cove, can't expect much.

 

[IntelUser2000]

Probably. Seems to basically just be RWC on Intel 3. Maybe they'll make a few tweaks, but if they didn't even bother to give it a new name like they did Raptor Cove, can't expect much.

2021 with the new node naming and announcement of IDM 2.0 and 20A process that Granite Rapids was put as Intel 4.

2022 was when Granite Rapids was moved to Intel 3. Are you sure about what you are saying, that they did not change the core? Since that's a 2021 slide?

 

[Exist50]

2021 with the new node naming and announcement of IDM 2.0 and 20A process that Granite Rapids was put as Intel 4.

2022 was when Granite Rapids was moved to Intel 3. Are you sure about what you are saying, that they did not change the core? Since that's a 2021 slide?

I mean, if they changed it much, surely they would have given it a different name, right? Raptor Cove has next to no architectural changes, and they still gave it one. Seems like they're still following the naming convention of tying the core name to process. Related, but, what's the Atom core labeled in this Sierra Forest leak? SGL?

 

[IntelUser2000]

I mean, if they changed it much, surely they would have given it a different name, right? Raptor Cove has next to no architectural changes, and they still gave it one. Seems like they're still following the naming convention of tying the core name to process. Related, but, what's the Atom core labeled in this Sierra Forest leak? SGL?

I didn't notice that. Nice catch. "Sierra Glen"

Well ok, but the original Nehalem was based on Netburst, and they reused the name for the Core-based chip. Also, while a different team altogether, they called successor to Goldmont, Goldmont Plus. Yet the change was substantial and brought 30% per clock improvements. Most thought based on that it was maybe a 5% gain. Naming seems to follow a loose rule but otherwise arbitrary.

And they did that for Skymont. Rumor mills had it as a successor for a Core chip, not Atom/E core based.

The slides themselves doesn't seem like enough of evidence to say it's post-change. And that core would indeed be Redwood Cove. If the change is minimal then it would stand to reason the time when Pat claimed it was changed, either he was lying or they had a second Intel 3 core going.

Also, do you think the 80 core thing is current? Because 80 core = SP, 120 core = AP is exactly what MLID said(I don't watch his full video either. I just skip to the written part). I would think he based it on this slide. There is truth to what he says, just that it's dwarfed by rampant imagination and errors.

 

[Exist50]

And they did that for Skymont. Rumor mills had it as a successor for a Core chip, not Atom/E core based.

Skymont was always an Atom core name. Though that should be a particularly fun one.

Also, do you think the 80 core thing is current? Because 80 core = SP, 120 core = AP is exactly what MLID said(I don't watch his full video either. I just skip to the written part).

Yeah, it seems reasonable enough. Even from just a die size perspective, it's around what you'd expect from 2-3 large compute dies.

If the change is minimal then it would stand to reason the time when Pat claimed it was changed, either he was lying or they had a second Intel 3 core going.

I'm increasingly convinced that at some point, Intel wanted to move GNR to Lion Cove. It would make sense for them to want to use their latest core. But the delay of Arrow Lake into 2024 makes me wonder if Lion Cove itself is not having schedule issues. And there's one detail that would be hard to reconcile.

 

[Henry swagger]

View attachment 78646
Oh wow the slides keep on looking better and better

Chiplets are the future.. you get spectacular scalling with them 😉💻

 

[Markfw]

Chiplets are the future.. you get spectacular scalling with them 😉💻

So that is why AMD is blowing Intel away right now....Nice of you to point out that AMD is the future, and the future is now for them !

 

[Geddagod]

So that is why AMD is blowing Intel away right now....Nice of you to point out that AMD is the future, and the future is now for them !

this is top tier trolling rn

 

[eek2121]

true, but people like Jenson, Steve Jobs and Lisa are one of a kind CEOs. These people know where the industry is heading.

One look at the ARC team and you know its headed for nowhere. They spent months getting DX9 to work properly and the most popular DX9 game CSGO is now getting replaced with CS2 which is vulkan based. CSGO will no longer exist.

I bet you a whole cheese island that Nvidia knew CS2 was coming(After all it was leaked via Nvidia channels). Intel spent hyping up DX9 benchmarks with CSGO as being the primary example, later in 2023 Summer that will will no longer exist.

That is just one example.

Except CS:GO is not dead. CS2 is not out yet, and won’t be for a while. Even when it is released, I suspect it will run just fine on Intel cards.

Intel has to continue GPU development or they will become irrelevant. Note that this does not mean discrete gaming GPUs, however. Rather, strong integrated graphics and powerful compute boards. Both NVIDIA and AMD already have their own platforms, and NVIDIA is working on initiatives that would allow them to pull away server/cloud market share from Intel/AMD.

You don’t just turn a blind eye to that.

 

[Kepler_L2]

Probably. Seems to basically just be RWC on Intel 3. Maybe they'll make a few tweaks, but if they didn't even bother to give it a new name like they did Raptor Cove, can't expect much.

It is a different core.

 

[Geddagod]

Given how accurate the GNR mockup was on Intel's presentation, I also have to wonder if DMR is actually going to end up like this:

 

[Henry swagger]

Given how accurate the GNR mockup was on Intel's presentation, I also have to wonder if DMR is actually going to end up like this:
View attachment 78661

No leaks of diamond rapids ?

 

[BorisTheBlade82]

Given how accurate the GNR mockup was on Intel's presentation, I also have to wonder if DMR is actually going to end up like this:
View attachment 78661

TBH, I expect one of the next EPYC to look a bit like this.

I made up a drawing a while ago:
The total area is exactly the on-package-area that a full blown Genoa occupies (so that caps and stuff still get the same space as now). Die area numbers are just exactly Genoa and will surely change. Geometries were modified in order to fit everything and get enough beachfront (not sure about the split IOD connection though).
Have fun dismissing this armchair engineer's work 😉

 

[Exist50]

It is a different core.
View attachment 78655

What are those files for/from? Server RWC will obviously have the AVX512 and AMX support we see in GLC server vs client, but the core uarch should be functionally identical.

 

[JoeRambo]

The total area is exactly the on-package-area that a full blown Genoa occupies (so that caps and stuff still get the same space as now). Die area numbers are just exactly Genoa and will surely change. Geometries were modified in order to fit everything and get enough beachfront (not sure about the split IOD connection though).
Have fun dismissing this armchair engineer's work 😉

Can AMD fit 16 chiplets? That's for sure, but the chiplet power tax will be there. Right now they can easily afford, just like they were able to afford it with 8 chiplet zen2/3 products.
But it has its power price, Zen2 era chiplets were like 16-25w a piece in fully loaded chip and IOD was 100w+ monster.

What happens IF Intel closes process gap and has MCs on compute dies? Despite naming, nothing in Infinity fabric is infinite and they chew power.

 

[BorisTheBlade82]

Can AMD fit 16 chiplets? That's for sure, but the chiplet power tax will be there. Right now they can easily afford, just like they were able to afford it with 8 chiplet zen2/3 products.
But it has its power price, Zen2 era chiplets were like 16-25w a piece in fully loaded chip and IOD was 100w+ monster.

What happens IF Intel closes process gap and has MCs on compute dies? Despite naming, nothing in Infinity fabric is infinite and they chew power.

tl;dr: There is no universal chiplet tax - just different physical Interconnect implementations.

That is why they need to change the physical Interconnect. My mock-ups had InFO-RDL in mind - 0.3pJ/bit compared to around 2pJ/bit for IFoP. That is only 15% power consumption for the same bandwidth.
Just to point out again: The IOD only consumes that much power, because it has to drive the IFoP.
There is nothing superior about what Intel is doing or will be doing in the short term about their DC tile strategy. They seem to have lost focus of what really matters.

Please see this article for reference:

Sapphire Rapids: Golden Cove Hits Servers

Last year, Intel’s Golden Cove brought the company back to competitive against AMD.

chipsandcheese.com

 

[JoeRambo]

There is nothing superior about what Intel is doing or will be doing in the short term about their DC tile strategy. They seem to have lost focus of what really matters.

AMD is playing the same card since Zen2 and is riding TSMC process advantage. I think their real current innovation and advantage in packaging is 3D cache. Very substantial one.

As customer i don't care how much Intel or AMD pay for their silicon, i leave that to their beancounters. As long as they both sell competitive chips for right price they can go for each others throat, i don't care.

Everything for Intel rides on their ability to fix process issues and ability to execute on roadmap. We already see the signs of AMD reacting in "hybrid" core introduction and hopefully You are right that they will rework IO part. But as long as MC is away from compute die and L3 is sharded they will continue to pay power/perf taxes.

The "my workload does not communicate between threads much" part of AMDs "lets increase count of chiplets" business advantage dissapears when Intel introduces their own "Atom" driven horde of cores.

 

[BorisTheBlade82]

AMD is playing the same card since Zen2 and is riding TSMC process advantage. I think their real current innovation and advantage in packaging is 3D cache. Very substantial one.

As customer i don't care how much Intel or AMD pay for their silicon, i leave that to their beancounters. As long as they both sell competitive chips for right price they can go for each others throat, i don't care.

Everything for Intel rides on their ability to fix process issues and ability to execute on roadmap. We already see the signs of AMD reacting in "hybrid" core introduction and hopefully You are right that they will rework IO part. But as long as MC is away from compute die and L3 is sharded they will continue to pay power/perf taxes.

The "my workload does not communicate between threads much" part of AMDs "lets increase count of chiplets" business advantage dissapears when Intel introduces their own "Atom" driven horde of cores.

I am not sure, I can follow you.
It is not only a question of processes, but also the general approach. AMD's star scheme with their IOD is so simple, yet beautiful.
No gigantic bandwidth needed between CCDs because they all share the same universal MC. And the diminishing returns of using remote Caches simply is not worth it.

Don't you realize that Intel pays for their EMIB a similar price in consumption, just because they need truckloads of bandwidth in order to make their topology work at all?
And although Intel can watch and examine this in the public since 2019, they seemingly do not grasp it.
Even Siera Forest (sic?) will keep a similarly awkward topology.

 

[Joe NYC]

Can AMD fit 16 chiplets? That's for sure, but the chiplet power tax will be there. Right now they can easily afford, just like they were able to afford it with 8 chiplet zen2/3 products.
But it has its power price, Zen2 era chiplets were like 16-25w a piece in fully loaded chip and IOD was 100w+ monster.

Using RDL / fanout cuts down the power usage significantly. Using it in client (one of the pictures @BorisTheBlade82 ) would be quite easy, but I have my doubts it would scale to the server chip.

 

[Joe NYC]

What happens IF Intel closes process gap and has MCs on compute dies? Despite naming, nothing in Infinity fabric is infinite and they chew power.

Infinity Fabric is the name of the protocol, IFOP (SerDes implementation of Infinity Fabric) is one of the implementations. It may be running out of steam, going to Zen 5, we will see if AMD makes any changes.

 

[JoeRambo]

No gigantic bandwidth needed between CCDs because they all share the same universal MC. And the diminishing returns of using remote Caches simply is not worth it.

Don't you realize that Intel pays for their EMIB a similar price in consumption, just because they need truckloads of bandwidth in order to make their topology work at all?

We had this type of discussion already with Alder Lake, Intel seemed to have very stupid L3 cache setup. Very high latency for size compared to AMD. Fast forward to RPL, and suddenly their L3 is performing better due to larger L2 cache shielding it from traffic and much faster uncore speeds.
What we have with SPR is compromise of anemic L3 cache that does not show up in action. If they are able to increase the size substantially in the future they will reap the benefits, cause the latency price is already paid.

So Intel's chip level architecture is more advanced now and if they can throw way more transistors in the form of cores and caches, they will have performant chip. That rests on their process execution ability.