Discussion Intel current and future Lakes & Rapids thread

[lightmanek]

Still didn't impact their ability to sell Alder Lake laptops. They will do fine. AMD Zen3+ laptops are still not available at the lower price points where ADL-mobile makes more sense to buy.

Anecdotal evidence, but there seems to be a good supply of Lenovo P16s AMD 6850U laptops in UK. I've bought one for under £900 with taxes just a week ago.

Lenovo ThinkPad P16s Gen 1 - 16 - AMD Ryzen 7 Pro 6850U - AMD PRO - 16 GB RAM - 512 GB SSD - UK | The IT Bay

Lenovo ThinkPad P16s Gen 1 21CK - 180-degree hinge design - AMD Ryzen 7 Pro 6850U / 2.7 GHz - AMD PRO - Win 10 Pro 64-bit (includes Win 11 Pro Licence) - Radeon 680M - 16 GB RAM - 512 GB SSD TCG Opal Encryption 2, NVMe, Value - 16" IPS 1920 x 1200 - 802.11a/b/g/n/ac/ax (Wi-Fi 6E) - black - kbd...

www.theitbay.com

 

[igor_kavinski]

I've bought one for under £900 with taxes just a week ago.

That's way more than I would want to spend on a laptop (unless it's a gaming laptop with a discrete GPU). My budget is usually under $600 and there's rarely a good AMD laptop available in that price range. I might go for a Zen 4 V-cache laptop or maybe a Zen 5 laptop in future if I can find that for under $800.

 

[Mopetar]

By the way, a prediction. Next CEO after Pat Gelsinger is gonna be Raja Koduri.

I'd short the stock so hard it'd make that whole GameStop fiasco from the other year look like a candy land day trader kiddie game by comparison.

 

[DrMrLordX]

Seems to be far more about Intel's monolithic, single ring design than anything process or [CPU] design related.

Golden/Raptor Cove is quite large for its performance profile. Even if they went chiplet, there would be area and power problems from using more than 8c.

Yet they're empirically quite useful for scenarios where you'd want >8c to begin with.

Which explains why Sapphire Rapids and Emerald Rapids make use of them. Er wait, no they don't. Even Granite Rapids won't be using e-cores.

 

[igor_kavinski]

Which explains why Sapphire Rapids and Emerald Rapids make use of them. Er wait, no they don't. Even Granite Rapids won't be using e-cores.

You have a point there!

 

[Exist50]

Which explains why Sapphire Rapids and Emerald Rapids make use of them. Er wait, no they don't. Even Granite Rapids won't be using e-cores.

They're making an entire new server line with them. It's absurd to deny their usefulness. The only real argument you can make is that it's taken Intel far too long to make such an obvious move. The ARM folk realized this ages ago.

I swear, some people are just in denial about hybrid and small cores.

 

[nicalandia]

ONNX 1.4 adds AMX Support for Sapphire Rapids 8490H

Microsoft ONNX Runtime 1.14 Released With A Big Intel AMX Performance Optimization - Phoronix

www.phoronix.com

Here Compared with 7950X



ONNX 1.4 Benchmark 8490H vs 7950X

 

[Markfw]

They're making an entire new server line with them. It's absurd to deny their usefulness. The only real argument you can make is that it's taken Intel far too long to make such an obvious move. The ARM folk realized this ages ago.

I swear, some people are just in denial about hybrid and small cores.

When you look at the performance of Genoa (all big cores) it kind of blows "hybrid and small cores" to bits. That could be why you say some of us are in denial.

And Genoa still no where close to Intel's P-cores in perf/watt, they rule that too.

 

[moinmoin]

Here Compared with 7950X

View attachment 76339

ONNX 1.4 Benchmark 8490H vs 7950X

With your pts charts (which I appreciate) you really ought to add clearer notes of what we are actually looking at.

So "a" is 7950X (16c/32t) and the other is actually 2x 8490H (so 120c/240t). Honestly find that hard to believe, both the difference between the two chips as well as the difference between AMX and no-AMX. Are Intel chips so bad in ONNX?

 

[Exist50]

When you look at the performance of Genoa (all big cores) it kind of blows "hybrid and small cores" to bits.

Compared to what? There's no small core server CPU on the market from either Intel or AMD yet, but both have announced plans to offer them. Are you expecting Bergamo to be a failure?

Really, it's just simple math. Small cores provide more performance for equivalent area and power.

 

[lightmanek]

That's way more than I would want to spend on a laptop (unless it's a gaming laptop with a discrete GPU). My budget is usually under $600 and there's rarely a good AMD laptop available in that price range. I might go for a Zen 4 V-cache laptop or maybe a Zen 5 laptop in future if I can find that for under $800.

I though your point was no availability at reasonable price. That laptop model is way cheaper than intel 12th gen equivalents and previous price for it was over £1500 so my conclusion is, availability is improving and small price war is starting in this price range.
This laptop is a proper business machine, has great 16:10 screen and excellent keyboard and trackpad, things important for work. Just wait short while for more brands and models to start getting back in stock, prices will fall

 

[Markfw]

Compared to what? There's no small core server CPU on the market from either Intel or AMD yet, but both have announced plans to offer them. Are you expecting Bergamo to be a failure?

Really, it's just simple math. Small cores provide more performance for equivalent area and power.

Genoa vs Bergamo is not in the same league as Intel P-core and E-core. E-core is 1/4th the size of P-cores, and way difference functionally. Here is what AT said about them:
"This means that these two cores, while functionally identical, will use different sets of masks. The Zen 4c core has been redesigned to have the same functionality but offer more density combined with a different power/performance point on the voltage frequency curve. This is going to affect power consumption, efficiency, and likely the range of frequencies available. "

So, they will both have AVX-512 and all the other things, but (for example) a Zen 4 core may run 2.4-3.7 ghz, while the Zen4c may run 2.0-3.0 and the power envelope may be 360 vs 250. They are different, but they are not big vs small cores. And the size difference is like ~30% vs 400% for E to P cores. And Zen4 and Zen4c in the same chip ? Not on the roadmap that I know of.

 

[controlflow]

Load power efficiency of RPL mobile is pretty impressive. Not entirely shocking of course, running many core at a more modest clock will result in better throughput than running a higher frequency on fewer cores all things equal. Hopefully they work on the idle power. This is a good result given the node disadvantage.

 

[Geddagod]

Genoa vs Bergamo is not in the same league as Intel P-core and E-core. E-core is 1/4th the size of P-cores, and way difference functionally. Here is what AT said about them:
"This means that these two cores, while functionally identical, will use different sets of masks. The Zen 4c core has been redesigned to have the same functionality but offer more density combined with a different power/performance point on the voltage frequency curve. This is going to affect power consumption, efficiency, and likely the range of frequencies available. "

So, they will both have AVX-512 and all the other things, but (for example) a Zen 4 core may run 2.4-3.7 ghz, while the Zen4c may run 2.0-3.0 and the power envelope may be 360 vs 250. They are different, but they are not big vs small cores. And the size difference is like ~30% vs 400% for E to P cores. And Zen4 and Zen4c in the same chip ? Not on the roadmap that I know of.

Aren't the purpose of AMD and big vs little cores pretty much the same though? Higher compute density vs Higher core per core performance. Yes AMD isn't making a whole new lineup, but that's because AMD prob didn't want to design an entirely new core for their "small" cores (design cost). Intel on the other hand has been making atom cores for a while before they integrated it into a hybrid architecture, so they probably ran with it.
There are merits to what Intel is doing vs what AMD is doing. There are drawbacks, a major one being cost, but I think Intel's method has way more design flexibility. Intel's small cores can be designed without caring about how they scale at 5 or 6 Ghz while AMDs zen architectures have to worry about scaling at high clocks. Intel big cores have to worry about both too though, so the only real advantage from this method is when it comes to designing Intel's small cores IMO.

 

[Geddagod]

Load power efficiency of RPL mobile is pretty impressive. Not entirely shocking of course, running many core at a more modest clock will result in better throughput than running a higher frequency on fewer cores all things equal. Hopefully they work on the idle power. This is a good result given the node disadvantage.

View attachment 76346

I would love to see ST power scaling or also Big core only MT power scaling. Unfortunately HWUB is already pumping out a lot of benchmarks, so I understand they prob won't have time, but still.
Nice scaling, but I wouldn't hold my breath with Dragon Range coming soon.
Could Dragon Range scale worse at higher power levels but be more efficient overall and also though because of fewer physical cores?
Something like this... just my guess
(you're welcome for the extremely crappy graph)

 

[Geddagod]

Also anyone know what Ocean Cove was supposed to be? Just randomly remembered it... cancelled architecture for MTL. Was it supposed to be a new arch vs GLC refresh that MTL is now? Cancelled a while back wasn't it? 2 or 3 years ago IIRC

 

[Hulk]

Is it even remotely possible for us to agree on IPC increases from past generations? And for those of you who don't like the word "IPC" we mean rate of work done at equal frequencies, or throughput at equal frequencies, etc...

A couple of years ago I compiled some benchmarks, normalized clocks, and calculated some percentages. Yes, I know normalizing clocks isn't great as memory doesn't scale, and yes I know there are a million benches out there, I tried to mainly stay with Anandtech. This is what I got. Support attached. You can see Intel pretty much works on one end then the other...

Intel Generational Work Rate Comparison Results	Geomean	Average
P4 to Conroe	82.7%	83.4%​	Complete redesign
Conroe to Nahalem	20.2%​	22.4%​	Memory increases, add L3
Nahalem to Sandy Bridge	11.8%​	12.2%​	Smarter OoO larger registers
Sandy Bridge to Ivy Bridge	6.7%​	6.9%​	Prefetcher improvements
Ivy Bridge to Haswell	8.7%​	8.9%​	add 2 execution ports
Haswell to Skylake	8.9%​	9.5%​	add simple decoder
Skylake to Sunny Cove	21.0%​	21.3%​	add 2 execution ports

 

[Geddagod]

Is it even remotely possible for us to agree on IPC increases from past generations? And for those of you who don't like the word "IPC" we mean rate of work done at equal frequencies, or throughput at equal frequencies, etc...

A couple of years ago I compiled some benchmarks, normalized clocks, and calculated some percentages. Yes, I know normalizing clocks isn't great as memory doesn't scale, and yes I know there are a million benches out there, I tried to mainly stay with Anandtech. This is what I got. Support attached. You can see Intel pretty much works on one end then the other...

Intel Generational Work Rate Comparison Results	Geomean	Average
P4 to Conroe	82.7%	83.4%​	Complete redesign
Conroe to Nahalem	20.2%​	22.4%​	Memory increases, add L3
Nahalem to Sandy Bridge	11.8%​	12.2%​	Smarter OoO larger registers
Sandy Bridge to Ivy Bridge	6.7%​	6.9%​	Prefetcher improvements
Ivy Bridge to Haswell	8.7%​	8.9%​	add 2 execution ports
Haswell to Skylake	8.9%​	9.5%​	add simple decoder
Skylake to Sunny Cove	21.0%​	21.3%​	add 2 execution ports

Wow this is actually a really cool collection and normalization of data you have here. Thank you.
The only thing I have to say is that (beyond the already mentioned weaknesses you have outlined in your methodology) is that a couple of interesting generations are missing. Palm Cove would have been extremely interesting to analyze.
Also I feel like the architectural changes should be expanded a bit. Changes in stuff like OOO size would also be a nice addition, for example, without having to blow up how much detail you include.
I also believe you could add an extra table including Intel's own IPC increase figures. To my knowledge, Intel usually uses spec or a wide variety of tests for their IPC testing, so I think it could be pretty reliable, and so far I don't think they outrageously lied about any IPC increases like they do with gaming averages or stuff like that.

 

[Hulk]

Wow this is actually a really cool collection and normalization of data you have here. Thank you.
The only thing I have to say is that (beyond the already mentioned weaknesses you have outlined in your methodology) is that a couple of interesting generations are missing. Palm Cove would have been extremely interesting to analyze.
Also I feel like the architectural changes should be expanded a bit. Changes in stuff like OOO size would also be a nice addition, for example, without having to blow up how much detail you include.
I also believe you could add an extra table including Intel's own IPC increase figures. To my knowledge, Intel usually uses spec or a wide variety of tests for their IPC testing, so I think it could be pretty reliable, and so far I don't think they outrageously lied about any IPC increases like they do with gaming averages or stuff like that.

Yes, there are a lot of issues with it. The big one is Rocket Lake wasn't out yet so I compared Sunny Cove to Skylake using mobile versions.

I have detailed architectural notes but it would be too much data for this presentation. Those notes were just the most fundamental changes.

 

[Hulk]

Okay, this one is even worse than the other. Just a pet project of mine over the years to try and track things.

Red font indicates changes from previous generation.

 

[semiman]

Genoa vs Bergamo is not in the same league as Intel P-core and E-core. E-core is 1/4th the size of P-cores, and way difference functionally. Here is what AT said about them:
"This means that these two cores, while functionally identical, will use different sets of masks. The Zen 4c core has been redesigned to have the same functionality but offer more density combined with a different power/performance point on the voltage frequency curve. This is going to affect power consumption, efficiency, and likely the range of frequencies available. "

So, they will both have AVX-512 and all the other things, but (for example) a Zen 4 core may run 2.4-3.7 ghz, while the Zen4c may run 2.0-3.0 and the power envelope may be 360 vs 250. They are different, but they are not big vs small cores. And the size difference is like ~30% vs 400% for E to P cores. And Zen4 and Zen4c in the same chip ? Not on the roadmap that I know of.

AMD is introducing Zen 4c to fight computing densities. Either AMD's using simliar designs or not is not really important for customers. They're aiming for the same market.
Even today, hypothetical Saphhire rapids-sized chip with Gracemont will pack up 180 cores (Assuming 3 GM cores per 1 GC core for conservative approaches). Zen 4c based chips will need to fight against a battalion of next mont CPUs, it'll be tough opponent.

 

[BorisTheBlade82]

Aren't the purpose of AMD and big vs little cores pretty much the same though? Higher compute density vs Higher core per core performance. Yes AMD isn't making a whole new lineup, but that's because AMD prob didn't want to design an entirely new core for their "small" cores (design cost). Intel on the other hand has been making atom cores for a while before they integrated it into a hybrid architecture, so they probably ran with it.
There are merits to what Intel is doing vs what AMD is doing. There are drawbacks, a major one being cost, but I think Intel's method has way more design flexibility. Intel's small cores can be designed without caring about how they scale at 5 or 6 Ghz while AMDs zen architectures have to worry about scaling at high clocks. Intel big cores have to worry about both too though, so the only real advantage from this method is when it comes to designing Intel's small cores IMO.

While I agree with most points, Zen4c IMHO should be considered to be the starting point for AMD's little line. When Zen5 arrives, the gap might widen by a lot. I hope that AMD will do their best to try and keep the ISA (including extensions) identical. Furthermore I believe that AMD will want to achieve real efficiency advantages for their little cores just like Apple (and just NOT like Intel).

 

[IntelUser2000]

@HurleyBird Good chart, but perf/clk gain is single threaded. Nehalem's real gain is ~5%. It has absurd gains in MT and in very memory bound apps but that's not really uarch. It's like a mild version of adding accelerators.

Sandy Bridge is close to 15% when you consider tests that used SSDs versus that used HDDs. It was a transitional period.

Also Sandy Bridge brought lots of new features. uop cache, Physical Registers, using same ports to save area power on the AVX execution, unifies the two level branch predictor into something slightly larger but back to one level.

Ivy Bridge added pretty much a single feature which is better FP divider. Haswell was just an expansion. Skylake was little more but still a middling performance gain.

Sunny Cove didn't add anything new but was a big uarch expansion.

 

[igor_kavinski]

Okay, this one is even worse than the other. Just a pet project of mine over the years to try and track things.

Red font indicates changes from previous generation.

SUPERB!

Do you have data on AMD too?

You really should make your own website with the data you have, especially if it can allow comparisons between CPUs.

 

[Saylick]

Is it even remotely possible for us to agree on IPC increases from past generations? And for those of you who don't like the word "IPC" we mean rate of work done at equal frequencies, or throughput at equal frequencies, etc...

A couple of years ago I compiled some benchmarks, normalized clocks, and calculated some percentages. Yes, I know normalizing clocks isn't great as memory doesn't scale, and yes I know there are a million benches out there, I tried to mainly stay with Anandtech. This is what I got. Support attached. You can see Intel pretty much works on one end then the other...

Intel Generational Work Rate Comparison Results	Geomean	Average
P4 to Conroe	82.7%	83.4%​	Complete redesign
Conroe to Nahalem	20.2%​	22.4%​	Memory increases, add L3
Nahalem to Sandy Bridge	11.8%​	12.2%​	Smarter OoO larger registers
Sandy Bridge to Ivy Bridge	6.7%​	6.9%​	Prefetcher improvements
Ivy Bridge to Haswell	8.7%​	8.9%​	add 2 execution ports
Haswell to Skylake	8.9%​	9.5%​	add simple decoder
Skylake to Sunny Cove	21.0%​	21.3%​	add 2 execution ports

Oooo. Me likey. Do you have plan on adding Golden Cove to the mix?