Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

Let me put it this way, Threadripper is more or less the ideal product.

Yes, but due to lack of Competition and other factors(like prioritizing higher margin products like EPYC) AMD HEDT has fallen back almost an entire generation(For AMD, but a full generation for Intel)

7950X and 13900K/S will be as good as medium sized Workstation CPUs(Zen3/Alder Lake 24/32 low clocked)

 

[Exist50]

Yeah, I don't doubt that. That conclusion is more a consequence of how large the P cores are and/or how small the E cores are. If that relationship didn't exist, it would be more feasible to do a configuration where you have more P cores than E cores.

Sure, but that relationship not only does exist, but is fundamental to the value proposition E cores offer in the first place.

 

[Timmah!]

Yes, but due to lack of Competition and other factors(like prioritizing higher margin products like EPYC) AMD HEDT has fallen back almost an entire generation(For AMD, but a full generation for Intel)

7950X and 13900K/S will be as good as medium sized Workstation CPUs(Zen3/Alder Lake 24/32 low clocked)

They will be, because there wont be anything better (for acceptable price).

 

[nicalandia]

They will be, because there wont be anything better (for acceptable price).

For general purpose computer yes, absolutely. Also take into account that Intel SPR has SDSi where if you need AVX512 and AMX you will have to pay to unlock them. And on Zen4(Ryzen 7/9) they will be standard

 

[Exist50]

take into account that Intel SPR has SDSi where if you need AVX512 and AMX you will have to pay to unlock them.

Source?

 

[nicalandia]

Source?

YuuKi_AnS, his QS sample 8480+(56C/112T) and 8490H(60C/120T) have it disabled by Paid For Software Lock.

 

[Exist50]

YuuKi_AnS, his QS sample 8480+(56C/112T) and 8490H(60C/120T) have it disabled by Paid For Software Lock.

Doesn't mean all SPR chips would be the same. That's very much a server thing, and probably doesn't even apply universally there.

 

[nicalandia]

Doesn't mean all SPR chips would be the same. That's very much a server thing, and probably doesn't even apply universally there.

While YuuKi_AnS only works with 2S, 4S and 8S system. I find it strange that the Server CPUs will have AVX512/AMX Disabled by SDSi and the Xeon W9 series will not...!


Edit.

Now that I remember the most recent Xeon W9 vs ThreadRipper "Preview" posted by Sisoftsandra. They mentioned the Sapphire Rapids being 34% higher on AVX512(Native Quad-Float/FP128 Multi-Media) due to that. So perhaps there is some light at the end of the tunnel.?





I believe that The lower than expected performance on the 8480+ on Geekbench is due to a locked AVX512

 

[nicalandia]

Look what I just found...!!

Details for Genuine Intel CPU 0000%@32C/64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3

Details for Result ID Genuine Intel(R) CPU 0000%@ (32C 64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3)

ranker.sisoftware.co.uk

The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?

 

[jpiniero]

The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?

Nah it's still SPR. Just a reduced core count but most of the L3 still intact.

 

[nicalandia]

Nah it's still SPR. Just a reduced core count but most of the L3 still intact.

I have never seen this kind of segmentation done by Intel, when they disable cores, they also disable the half ring connected to that core, that is done to reduce Power and performance latencies penalties.. The Leaked SKUs do not show any other SPR with higher MiB per core.

 

[nicalandia]

4S Sapphire Rapids Geekbench.

Supermicro SYS-621H-TN12R - Geekbench

Benchmark results for a Supermicro SYS-621H-TN12R with an Intel Xeon Platinum 8468 processor.

browser.geekbench.com

 

[Tuna-Fish]

I have never seen this kind of segmentation done by Intel, when they disable cores, they also disable the half ring connected to that core, that is done to reduce Power and performance latencies penalties.. The Leaked SKUs do not show any other SPR with higher MiB per core.

I believe they have done this in the past for some "license-optimized" SKUs. That is, fastest-running chips off the line with most of the cores fused off but leaving all the cache which are then auctioned to interested parties, who run Oracle or something else similar on them where the software licensing is per core (so you want fastest possible cores but low core count and all the cache and memory bandwidth).

 

[Markfw]

I don't have geekbench numbers memorized. Is 21, 799 for 192 threads good ? does not sound like it.

I just looked. 2 32 core 64 thread (128t total) Zen 4 was 57,xxx (something), so 21799 for 192 is dismal.

 

[Exist50]

Look what I just found...!!

Details for Genuine Intel CPU 0000%@32C/64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3

Details for Result ID Genuine Intel(R) CPU 0000%@ (32C 64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3)

ranker.sisoftware.co.uk

The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?

That's an interesting find. Provided it's being read correctly, I can believe it's Emerald Rapids. Don't see why monolithic SPR would have any more L3/core than chiplet. Will certainly be interesting to see what the die looks like.

 

[nicalandia]

I don't have geekbench numbers memorized. Is 21, 799 for 192 threads good ? does not sound like it.

I just looked. 2 32 core 64 thread (128t total) Zen 4 was 57,xxx (something), so 21799 for 192 is dismal.

Dont put too much weight on early Geekbench results. The First ones for Genoa were dismal, but that's because Geekbench. The very early results are good to see uArch info.

 

[jpiniero]

I have never seen this kind of segmentation done by Intel, when they disable cores, they also disable the half ring connected to that core, that is done to reduce Power and performance latencies penalties.. The Leaked SKUs do not show any other SPR with higher MiB per core.

See the Xeon 6256 from Cascade Lake. Only 12 cores but it has 33 MB of the 38.5 MB L3.

 

[nicalandia]

Perhaps Emerald Rapids is on track for a Q2 2024 Release?

https://twitter.com/x/status/1565271083908861952

 

[DrMrLordX]

Less talk, more action, Intel.

 

[moinmoin]

Ian gets to the main point.

https://twitter.com/x/status/1565273568480477184

 

[jpiniero]

Less talk, more action, Intel.

Yeah. Intel's said similar things about 10 nm AND 7 nm.

 

[uzzi38]

Perhaps Emerald Rapids is on track for a Q2 2024 Release?

https://twitter.com/x/status/1565271083908861952

View attachment 66944

Pretty sure we've already established that launch SPR silicon for the majority of the market is E5 stepping, no?

 

[jpiniero]

Pretty sure we've already established that launch SPR silicon for the majority of the market is E5 stepping, no?

Does that one have the UPI bug fixed? Because that one is critical.

 

[Exist50]

Perhaps Emerald Rapids is on track for a Q2 2024 Release?

They better start shipping it H2'23. There's really no excuse for effectively a refresh product to take longer than a year.

But I agree with Ian. We've heard the same song and dance before. I can believe that GNR will take fewer steppings, but it's already been significantly delayed, and I have little confidence that the program is better managed.

 

[nicalandia]

They better start shipping it H2'23. There's really no excuse for effectively a refresh product to take longer than a year.

It's a little bit more than a Refresh. They have Raptor Cove P cores on it. Larger Cache and Larger Compute Tile(64C/128T) Total, Larger HBM2e. All of those need validation.