Discussion Intel current and future Lakes & Rapids thread

[Exist50]

A full unrestrained Raptor Cove vs Genoa Would be an amazing match. 64C/128T With 192 MiB L3. But instead the best Sapphire Rapids will bring 60C/120T with 112 MiB..

Chips and Cheese made Cache System Simulation and Alder Lake gains IPC just by encreasing the shared L3 from 30 MiB to 36 MiB, and that happens to be Raptor Lake.

Going Armchair Quarterback on Golden Cove’s Caches

Processor speed has rapidly outpaced advances in DRAM technology, so caching strategy is a huge part of CPU performance today. A couple of articles ago, we saw Intel’s decisions with Golden C…

chipsandcheese.com

More cache would be better for a number of workloads, sure, but it wouldn't work miracles. There's pretty much nothing that could be done to make Sapphire Rapids competitive with Genoa. Just a long, long wait to Granite or Diamond Rapids...

 

[nicalandia]

More cache would be better for a number of workloads, sure, but it wouldn't work miracles. There's pretty much nothing that could be done to make Sapphire Rapids competitive with Genoa. Just a long, long wait to Granite or Diamond Rapids...

Its a design choice. Golden/Raptor Cove has a huge penalty for L2/L3 cache Misses. They are banking on HBM on package memory to reduce the very expensive trip to main memory acess.

For desktop they have Large 3MiB of L3 per Core to mitigate that on Raptor Cove cores that extends to 4.5 MiB on many worloads


But on HCC and most 1S/2S System they are left with an enemic paltry 1.8MiB per core.

 

[Exist50]

They are banking on HBM on package memory to reduce the very expensive trip to main memory acess.

HBM is a niche product for AI workloads. Has nothing to do with the choice of L3.

 

[nicalandia]

Double post.

 

[nicalandia]

HBM is a niche product for AI workloads. Has nothing to do with the choice of L3.

Just about any app can benefit from the HBM as L3 because it's transparent to software no need to code.



HBM As LLC/L3

When the processor is booted in Cache mode all or a part of the HBM is used as cache. HBM cache is treated as a Last Level Cache (LLC/L3), which is located between MLC/L2 cache and addressable memory in the memory hierarchy. HBM caches the entire physical address space, and is itself cached by L2

The advantage of using the HBM as cache is that it is managed by the platform and is transparent to software. So no action is required for the developer to use the HBM in an application, which makes HBM as cache effective for developers unfamiliar with memory performance tuning, or for applications that are difficult to tune.




But most Xeons and the SPR Xeons W HEDT CPUs will lack HBM and are left with a LLC/L3 constrained System

 

[IntelUser2000]

Just about any app can benefit from the HBM as L3 because it's transparent to software no need to code.

Sure but the benefits are niche because it's not an on-die cache. It's latencies are much higher. Even the stacked SRAM of AMD chips are limited in benefit because at certain sizes the benefits just are'nt there.

 

[IntelUser2000]

So the earnings report is saying Intel lost sales and marketshare in client because low end sales evaporated. I am talking about sales to schools and such. Also it means AMD had little to no exposure.

According to third party data they lost lots of laptop share.

I know notebook losses are also driven by Alderlake mobile's significant regression in battery life. The idle power shot up significantly! I would avoid this generation personally for laptops.

 

[mikk]

Alder Lake failed in the mobile market, this is obvious by comparing the market adoption. For Intel standards it ramped very very slowly, Tigerlake ramped a lot faster. We are approaching September and ADL is so far off from Tigerlake it's a serious problem for them. In particular ADL-P/U where battery life is traditionally very important. I guess ADL-P/U will never really able to replace TGL-U. The problem also seems to be platform cost. ADL-P is basically a 1000+ EUR platform and ADL-U 800+ EUR. TGL-U is Intels last proper mobile CPU for the mass market.

ADL-H 226
ADL-P 103
ADL-U 149

TGL-H45 419
TGL-H35 104
TGL-U 1315

Notebooks Preisvergleich Geizhals Deutschland

Preisvergleich für Notebooks ✓ Bewertungen ✓ Produktinfos ⇒ Auswahl und Filtern der Produkte nach den besten Eigenschaften und dem billigsten Preis

geizhals.de

 

[coercitiv]

I know notebook losses are also driven by Alderlake mobile's significant regression in battery life. The idle power shot up significantly! I would avoid this generation personally for laptops.

Based on personal experience, the price tag is the bigger problem ATM. Laptops with TGL or Cezanne are shockingly cheaper than corresponding ADL or Rembrandt models. I think the market slowed down "unexpectedly" and clogged older inventory everywhere. There's plenty of TGL / Cezanne to be had with great discounts and great specs.

 

[LightningZ71]

Notably, there are a ton of laptops out there in the sub $400 market with the 1115g4. If you don't do anything special with your laptop except surf, write emails, the occasional spreadsheet or document, and play videos, that is a perfectly usable platform. It'll even do light gaming.

 

[Exist50]

Alder Lake failed in the mobile market, this is obvious by comparing the market adoption. For Intel standards it ramped very very slowly, Tigerlake ramped a lot faster. We are approaching September and ADL is so far off from Tigerlake it's a serious problem for them. In particular ADL-P/U where battery life is traditionally very important. I guess ADL-P/U will never really able to replace TGL-U. The problem also seems to be platform cost. ADL-P is basically a 1000+ EUR platform and ADL-U 800+ EUR. TGL-U is Intels last proper mobile CPU for the mass market.

ADL-H 226
ADL-P 103
ADL-U 149

TGL-H45 419
TGL-H35 104
TGL-U 1315

Notebooks Preisvergleich Geizhals Deutschland

Preisvergleich für Notebooks ✓ Bewertungen ✓ Produktinfos ⇒ Auswahl und Filtern der Produkte nach den besten Eigenschaften und dem billigsten Preis

geizhals.de

What ever happened with the native 2+8 die? Is it even available in products yet? I wonder if they've basically been using the 6+8 for everything thus far, as that would explain the high costs (and maybe even a bit of the power issue as well).

 

[guidryp]

What ever happened with the native 2+8 die? Is it even available in products yet? I wonder if they've basically been using the 6+8 for everything thus far, as that would explain the high costs (and maybe even a bit of the power issue as well).

Here's one:

https://www.notebookcheck.net/Intel-Core-i7-1265U-debut-Dell-Latitude-13-7330-1-kg-laptop-review.635255.0.html

 

[jpiniero]

What ever happened with the native 2+8 die? Is it even available in products yet? I wonder if they've basically been using the 6+8 for everything thus far, as that would explain the high costs (and maybe even a bit of the power issue as well).

Dell does have an XPS available using U9 so it's out there. How much of U15 is 6+8 salvage versus 2+8 is definitely questionable. And U15 is def more popular (with OEMs) than P.

 

[shady28]

Based on personal experience, the price tag is the bigger problem ATM. Laptops with TGL or Cezanne are shockingly cheaper than corresponding ADL or Rembrandt models. I think the market slowed down "unexpectedly" and clogged older inventory everywhere. There's plenty of TGL / Cezanne to be had with great discounts and great specs.

I've actually seen the major OEMs (Dell, HP, Lenovo) finally clear out the old Tiger Lake laptops in the past month or so. A couple of months ago I had looked and there were not many ADL laptops, now they are probably 90% of their online products. The OEMs probably discounted a ton of the Tiger Lake parts and sent them into retail channels is why they show up on Best Buy and Amazon now.

The server space, not so much. Bread and butter small HP and Dell servers are chock full of 14nm Cascade Lake Xeons. The AMD based ones like the HP DLXX5 servers (DLXX5 is AMD, DLXX0 is Intel) mostly have Zen 3 based EPYC 7300 series now in the midrange, and the Zen 2 based 72XX in low end servers. It looks to me like Ice Lake-SP never really arrived in the basic server arena, I don't see them outside of expensive HCI VM setups and edge / HPC systems. There will be some big write-downs if Intel's partners continue to hang onto these old platforms in their more basic offerings.

OTOH, there's that SQUIP problem with VMs able to spy on each on AMD platforms that may (will) become a big issue if not fixed quickly.

 

[nicalandia]

Sure but the benefits are niche because it's not an on-die cache. It's latencies are much higher. Even the stacked SRAM of AMD chips are limited in benefit because at certain sizes the benefits just are'nt there.

Its not much about benefit, but a way to mitigate the L3 imbalace on the Sapphire rapids design(due to the mesh design, the power requierements grow exponentially after 2MiB per core) the on package HBM will act as the LLC L4. L3 Capacity misses will go to the much faster On package HBM.

Interesting enough with DDR5 Optane SPR could have had a L5 Cache Hierarchy

On Die L3 112 MiB per 60 Core
On Package 64 GiB as L4(Adressable)
Allocated DDR5 DRAM as transparent L5(non-addresable)

Optane DCPMMs/DDR5 RAM combined as System memory.

I fully expect a HBM Only mode(No DDR5 DRAM sticks on MB) Sapphire Rapids will show the highest performance on general benchmarks due to the HBM being faster than off die DRAM and having a greater than 1 Tbs/s bandwith.

 

[itsmydamnation]

Its not much about benefit, but a way to mitigate the L3 imbalace on the Sapphire rapids design(due to the mesh design, the power requierements grow exponentially after 2MiB per core) the on package HBM will act as the LLC L4. L3 Capacity misses will go to the much faster On package HBM.

Interesting enough with DDR5 Optane SPR could have had a L5 Cache Hierarchy

On Die L3 112 MiB per 60 Core
On Package 64 GiB as L4(Adressable)
Allocated DDR5 DRAM as transparent L5(non-addresable)

Optane DCPMMs/DDR5 RAM combined as System memory.

I fully expect a HBM Only mode(No DDR5 DRAM sticks on MB) Sapphire Rapids will show the highest performance on general benchmarks due to the HBM being faster than off die DRAM and having a greater than 1 Tbs/s bandwith.

stop making crap up.

HBM is Dram, Slow clocked Dram at that!

caches do one of two things,
reduce latency
amplify bandwidth.

HBM acting as a cache will provide no latency benefit , infact misses to memory will probably be worse then if its acting as a scratch pad because extra latency on HBM cache miss.
What HBM will do is massively increase bandwidth which is why intel has shown bandwidth bound benchmarks so far.

This is no different then the previous knights family.

MCDRAM as High-Bandwidth Memory (HBM) in Knights Landing Processors: Developer’s Guide

This publication is part of a developer guide focusing on the new features in 2nd generation Intel® Xeon Phi™ processors code-named Knights Landing (KNL). In this document we discuss the…

colfaxresearch.com

 

[nicalandia]

stop making crap up.

Can you please point out what part of my post is not factually correct?

 

[lobz]

The latter, of course. Just saying, you are aware neither of those are the numbers for SPR/RPL, even on a core per basis, right? And then you need to consider that L3 is shared, and SPR has a lot more cores...

stop making crap up.

HBM is Dram, Slow clocked Dram at that!

caches do one of two things,
reduce latency
amplify bandwidth.

HBM acting as a cache will provide no latency benefit , infact misses to memory will probably be worse then if its acting as a scratch pad because extra latency on HBM cache miss.
What HBM will do is massively increase bandwidth which is why intel has shown bandwidth bound benchmarks so far.

This is no different then the previous knights family.

MCDRAM as High-Bandwidth Memory (HBM) in Knights Landing Processors: Developer’s Guide

This publication is part of a developer guide focusing on the new features in 2nd generation Intel® Xeon Phi™ processors code-named Knights Landing (KNL). In this document we discuss the…

colfaxresearch.com

ironically, the knight has fallen.... 🤣

 

[nicalandia]

Intel on board HMB2e/MCDRAM is so much better than DDR5 its not even a fair comparison(Latencies/Bandwidth)

 

[moinmoin]

ironically, the knight has fallen.... 🤣

It was a hard landing as well...

 

[nicalandia]

YuuKi_Ans is confirming that the 8S and S8S are comin...



But so far those 8S SPR-SP are currently on Stepping B, which means that late 2023 release is likely

 

[IntelUser2000]

Intel on board HMB2e/MCDRAM is so much better than DDR5 its not even a fair comparison(Latencies/Bandwidth)

We told you this already. HBM is about bandwidth. Latencies are no better. If it was, you can be sure Intel will be all over promoting it.

The fact is latencies benefit all, while bandwidth benefits are limited. An extra layer will also cause higher latency on a miss. Do you even know what a Miss is?

Also it's not a cache, as it requires tags. These don't. Even the superfast low latency large cache in VCache provides only limited benefits. HBM is entirely HPC play. The volume compared to non HBM versions will be negligible as it always has been. Nothing to do with Sapphire Rapids cache hierarchy.

 

[nicalandia]

We told you this already. HBM is about bandwidth. Latencies are no better. If it was, you can be sure Intel will be all over promoting it.

The fact is latencies benefit all, while bandwidth benefits are limited. An extra layer will also cause higher latency on a miss. Do you even know what a Miss is?

Also it's not a cache, as it requires tags. These don't. Even the superfast low latency large cache in VCache provides only limited benefits. HBM is entirely HPC play. The volume compared to non HBM versions will be negligible as it always has been. Nothing to do with Sapphire Rapids cache hierarchy.

How Often does Windows duplicate L3 Capacity? I have seen a screenshot of performance monitor with twice as much Capacity for a ES SPR-SP. Perhaps a Windows bug or HBM2e being adressed?

 

[DrMrLordX]

But so far those 8S SPR-SP are currently on Stepping B, which means that late 2023 release is likely

8S systems are extremely rare these days. Only a few select buyers want them. If that's the only place HBM2e Sapphire Rapids shows up, then it's not going to be terribly relevant compared to standard 1/2S Sapphire Rapids.

 

[Exist50]

But so far those 8S SPR-SP are currently on Stepping B, which means that late 2023 release is likely

You're conflating the two things. SPR-HBM is "only" on B step, while some version of SPR-SP will support 8S. Two independent things. For that matter, the HBM version shouldn't need as many steppings as the original, since it should leverage all the bug fixes.