Don't forget the Bulldozer was a complete redesign, too.
Bulldozer was a new design, not a redesign.
Of three new designs it was the mid-performance design:
Performance Core => Monolithic SMT2 core with HP co-processor on 45nm partially depleted strained silicon on insulator (
https://www.catrene.org/web/downloads/profiles_medea/2T101_profile.pdf )
Value Core => Cluster-based Multithreading with HiPerf co-processor on low-power/low-cost 45nm partially depleted silicon on insulator (1st Bulldozer)
Pervasive Core => Single-cluster architecture with LowPow co-processor but on extra-low-cost 65nm partially depleted silicon on insulator. (1st Bobcat)
Even if it is a a new design, Intel shouldn't have the issue of five different chief architects hot-potatoing the architecture.
AMD - K5-architect for Pre-Bulldozer (single-threaded clustered microarchitecture)
AMD - New team for Pre-Bulldozer (Low-power multithreaded clustered micro-architecture)
AMD - Glew gets involved in Pre-Bulldozer (Low-power -> High-performance, switches cluster-interconnect to something more difficult)
AMD - Moore gets involved (Switches multi-cluster interconnect to something simpler) - (1st Bulldozer M-SPACE scaled up from 1st Bobcat)
AMD/Microsoft - Butler+Microsoft guy (Switches from clusters to cores, Cluster-based Multithreading -> Chip-level Multithreading) - (2nd Bulldozer - Production)
I don't think a complete redesign or new design for P-core at Intel given above. Would ever be as that complex or end in a design which arbitrarily halves ST-perf.