Intel CSI -- What's the deal?

[ECX]

I've been trying to search the 'net for information regarding Intel's CSI technology, but unfortunately I can't seem to find much.

Does anybody know any specs of Intel's CSI? Also, how does it compare with AMD's hypertransport as of now?

Thanks!

-ECX

 

[Viditor]

Originally posted by: ECX
I've been trying to search the 'net for information regarding Intel's CSI technology, but unfortunately I can't seem to find much.

Does anybody know any specs of Intel's CSI? Also, how does it compare with AMD's hypertransport as of now?

Thanks!

-ECX

I don't have specs at hand, but in essence it will create a ring form of HT. It will do other things as well...CSI stands for Common Serial Interface, and we should (probably) see all Intel CPUs eventually using the same socket.
Little is known at the moment of the specifics...mainly because they haven't gotten it to work yet.
We know it's on the roadmap for 2009.

 

[BrownTown]

CSI is nothing more than a codeword for now, we have no information on any aspect of its workings. All that is known is that it is a point to point bus replacement for the current FSB. Obviously one would expect greater bandwidth between CPUs, or the CPU and the chipset. Apparently there are reports that Intel India was working on this technology and pretty much got over ambitious with their design and more or less have had to go back to the drawing board. Right now its a 2008 or later technology, and there is currently no timetable for delivery.

 

[Furen]

In my opinion there are two main things to CSI:

It's a serial interconnect, which should simplify routing in MP boards and allow point-to-point CPU connections instead of having all inter-cpu transfers hit a FSB hub (exactly like HT did for AMD).

It's propietary, which should allow Intel to keep its iron grip on its chipset market and makes sure that Intel's chipsets are only used on Intel CPU-based systems (the main drawback to AMD is that its chipsets are not Intel which, in my opinion, are the best ones out there).

 

[Viditor]

I do remember seeing a paper from Intel about CSI about a year ago, but I can't find it anymore...
One of my engineering friends helped to translate it for me.
Basically, it talked about a Token-Ring type of connection for the interconnects. This would (hopefully) decrease latency below that of even HT in multichip configurations.