Intel Capex: $16.2B, already building 14nm factories

[Phynaz]

Intel plans to spend $16.2 billion this year on a wide range of internal investments, up $500 million from earlier forecasts. The funds will fuel efforts in areas ranging from servers, notebooks, tablets, smartphones and enhancements to its 14nm fabs under construction.

"Some of [the increased fab expenses] are a pull-in from next year [because we are moving] faster than expected into our 14nm factories," said Stacy Smith, Intel's CFO in the conference call.

But "the larger portion is an increase in the scope of the factories," Smith said. The 14nm plants will now be outfitted to handle expected needs for 10 and 7nm process technology, he added.

"There's a higher return-on-investment to do that now rather than later," Smith said. Currently Intel's capex spending is focused on enabling "22nm peak [production] and [building] 14nm shells, and soon you'll see us move into the cycle of 14nm equipment" purchases, he said.

http://www.eetimes.com/electronics-news/4218047/Intel-boosts-capex-eyeing-7nm-node

 

[Idontcare]

The 14nm plants will now be outfitted to handle expected needs for 10 and 7nm process technology, he added.

I read this to imply they are gearing up for EUV deployment at 14nm.

 

[Phynaz]

Does that make them the first?

The only?

P.S. Welcome back!

 

[GammaLaser]

Really? Everything I've seen showed that Intel was going to stretch multiple patterning w/ immersion litho all the way down to 11nm. But EUV would be cool

 

[Idontcare]

Does that make them the first?

The only?

P.S. Welcome back!

For HVM yes, if it actually turns out to be the case.

Right now everyone in the top-10 has access to EUV equipment for R&D. IBM and GloFo have both made much progress in using EUV equipment, not unexpected given GloFo's accelerated adoption in HVM with immersion litho.

EUV makes sense for the companies that have massive volumes of a single product, like Intel or the memory companies (Toshiba, Micron, etc).

The maskset cost is so high though that the economics simply don't make sense for the bulk of the volumes that a foundry like TSMC (and presumably GloFo someday if they realize their goals). That is why you see/read/hear about TSMC pushing ebeam direct-write litho so much.

And not surprisingly it was TSMC that pushed the industry to develop immersion litho, that wasn't Intel or IBM...Intel killed 157nm litho but failed to offer an alternative, it was TSMC that stepped up and provided the leadership for industry direction at that point.

For that reason, TSMC's continued support for ebeam direct-write is given credence in the industry. But it makes little economic sense for the memory makers and any logic players who have large volumes of product generated from single mask sets like CPU's and GPU's.

 

[Nemesis 1]

This is why I am intel fan . They reinvest in the company and AMERICA.

 

[Idontcare]

Really? Everything I've seen showed that Intel was going to stretch multiple patterning w/ immersion litho all the way down to 11nm. But EUV would be cool

That's from a long time ago (Feb 2010).

There was a time period where Intel publicly portrayed 3D gate xtors as too risky for 22nm as well.

What I get out of the EETimes article is that they see a path to continuing to rely on immersion litho if needed down to 11nm.

Intel does all kinds of parallel pathfinding projects solely for the purpose of having options on the table to minimize the risks of uncontrollable events in their supply chain (such as EUV being delayed for any number of foreseeable reasons, or for one's that are unforeseen).

 

[GammaLaser]

That's from a long time ago (Feb 2010).

There was a time period where Intel publicly portrayed 3D gate xtors as too risky for 22nm as well.

What I get out of the EETimes article is that they see a path to continuing to rely on immersion litho if needed down to 11nm.

Intel does all kinds of parallel pathfinding projects solely for the purpose of having options on the table to minimize the risks of uncontrollable events in their supply chain (such as EUV being delayed for any number of foreseeable reasons, or for one's that are unforeseen).

Well, here is a newer (Feb 2011) article that confirms that it'll miss 14nm, but EUV still has a chance at 10nm. I wouldn't complain if it arrives ASAP though

 

[Spikesoldier]

This is why I am intel fan . They reinvest in the company and AMERICA.

did you see any mention in the article that any of the fabs would be in the US?

will give you that intel is a US company, matter of fact, its a component of the Dow Jones Industrial Average.

 

[GammaLaser]

did you see any mention in the article that any of the fabs would be in the US?

will give you that intel is a US company, matter of fact, its a component of the Dow Jones Industrial Average.

The 14nm fab is in Arizona.

 

[soccerballtux]

I read this to imply they are gearing up for EUV deployment at 14nm.

good luck pulling 14 off without euv, wouldn't they would have to have it unless they wanted to double pattern.

 

[WhoBeDaPlaya]

...That is why you see/read/hear about TSMC pushing ebeam direct-write litho so much....

Wouldn't throughput suffer though? Unless raster rates have improved significantly that is.

 

[Nemesis 1]

did you see any mention in the article that any of the fabs would be in the US?

will give you that intel is a US company, matter of fact, its a component of the Dow Jones Industrial Average.

Did I have to? I pick my horses carefully. Whats good for intel is in fact good for me and the USA. PERIOD.

 

[gevorg]

Just 5 more years!

Intel to launch Pelican Lake shrink on 7nm in 2016
http://www.kitguru.net/components/cpu/jules/intel-to-launch-pelican-lake-shrink-on-7nm-in-2016/

 

[PreferLinux]

Just 5 more years!

Intel to launch Pelican Lake shrink on 7nm in 2016
http://www.kitguru.net/components/cpu/jules/intel-to-launch-pelican-lake-shrink-on-7nm-in-2016/

I believe "Pelican" Lake was made up by Semiaccurate, and that it is actually Sky lake. Or at least according to them.

 

[Idontcare]

Wouldn't throughput suffer though? Unless raster rates have improved significantly that is.

At the risk of stating the obvious, there's a reason it isn't in production already

That said, of course there is steady progress made in the pursuit of bringing ebeam litho to market.

Here's a marketing blurb page by a company that sells the tools. They claim 5-10 wfrs per hour per module which is not great but if you are only printing 20wfrs for the entire life of a specific product then it can make sense to avoid the cost of the maskset altogether.

Last I heard they were working on a model that employed 10,000 beam lines in parallel (crazy to think they found a way to manipulate that many individual beam lines).

 

[Idontcare]

good luck pulling 14 off without euv, wouldn't they would have to have it unless they wanted to double pattern.

EUV is so far behind schedule that even EUV is expected to require double pattern when it finally debuts.

Consider that it has a 13.5nm wavelength. Sub-20nm half-pitch printing is going to require double pattern, even for EUV sources.

 

[khon]

Consider that it has a 13.5nm wavelength. Sub-20nm half-pitch printing is going to require double pattern, even for EUV sources.

Sorry, that's not correct.

Assuming the specs for the first EUV production tool (expected release date is next year), it will be possible to go down to 11nm half-pitch printing without double patterning.

And future EUV tools will almost certainly lower that further still.

 

[Idontcare]

Sorry, that's not correct.

Assuming the specs for the first EUV production tool (expected release date is next year), it will be possible to go down to 11nm half-pitch printing without double patterning.

And future EUV tools will almost certainly lower that further still.

That's great to hear. Has it been demonstrated or is it just a targeted spec at this point?

I refered to sub-20nm half-pitch as the cutoff point because that is what has been demonstrated in practice as far as I am aware, and it required double patterning to accomplish.

I was not in attendence at the latest SPIE though, was anything more advanced put forward? Can you link it for those of us who are interested?

 

[WhoBeDaPlaya]

Last I heard they were working on a model that employed 10,000 beam lines in parallel (crazy to think they found a way to manipulate that many individual beam lines).

Wow! That's pretty darned impressive!

 

[khon]

That's great to hear. Has it been demonstrated or is it just a targeted spec at this point?

I refered to sub-20nm half-pitch as the cutoff point because that is what has been demonstrated in practice as far as I am aware, and it required double patterning to accomplish.

I was not in attendence at the latest SPIE though, was anything more advanced put forward? Can you link it for those of us who are interested?

Sub-20nm half-pitch using single patterning has been demonstrated. Going all the way down to 11nm hasn't been done yet as far as I know, this is merely the theoretical limit for the NXE:3300 (first full production EUV tool from ASML).

I can give you a link, but fair warning, it's extremely technical:

http://www.lithoworkshop.org/pdfs/presentations/Meiling%20ASML%20EUV%20program%20final%20handout.pdf

(you can see the 11nm theoretical limit that I mentioned on slide 27)

Also shows the plans for going all the way down to sub-5nm with future EUV tools, though that's really very much conjecture at this point.

 

[Idontcare]

Sub-20nm half-pitch using single patterning has been demonstrated. Going all the way down to 11nm hasn't been done yet as far as I know, this is merely the theoretical limit for the NXE:3300 (first full production EUV tool from ASML).

I can give you a link, but fair warning, it's extremely technical:

http://www.lithoworkshop.org/pdfs/presentations/Meiling ASML EUV program final handout.pdf

(you can see the 11nm theoretical limit that I mentioned on slide 27)

Also shows the plans for going all the way down to sub-5nm with future EUV tools, though that's really very much conjecture at this point.

Thanks for the link :thumbsup:

FWIW they appear to only show examples of 24nm and 25nm half-pitch prints in that workshop handout, but I'll happily take your word for it that they have successfully printed sub-20nm half-pitch in-house and just haven't made it public domain info yet.

One thing I have contemplated about the EUV timeline is that while we can easily argue that the leading edge IDM's such as Intel and Toshiba/Samsung may well have already raced paced the easy-ground for EUV by way of litho tricks and magic with their immersion tools and computational lithography (tricks that can obviously be put to work with EUV as well, extending EUV's own viability too) but there is a large market out there of IDM's that are on a trailing edge which EUV could in theory be put to work to economical advantage of avoiding the tricks and magic that makes double-patterning immersion litho w/computational litho assist.

EUV may be absolutely required for Intel's 11nm node but it could also make it much more economical for a SMIC to roll out their 45nm node in the same timeframe by virtue of making the litho development process 10x easier to implement.

I'd be curious to know if ASML is seeing trailing-edge IDM's looking into immersion-litho tools for nodes like 65nm where dry-litho was more or less brute forced to work when the leading-edge IDM's worked through them years prior. (I know you can't comment, but I could see the economics actually working in favor of more advanced litho enabling older nodes to be economically viable inasmuch as the same advanced litho is critical in enabling advanced nodes at nearly any cost)

 

[OCGuy]

Very interesting read. I am enjoying the responses in this thread too. :thumbsup:

 

[khon]

Thanks for the link :thumbsup:

FWIW they appear to only show examples of 24nm and 25nm half-pitch prints in that workshop handout, but I'll happily take your word for it that they have successfully printed sub-20nm half-pitch in-house and just haven't made it public domain info yet.

If it wasn't public, I would not be saying anything. I'd never risk losing my job like that.

http://www.eetimes.com/electronics-news/4213730/ASML-claims-progress-in-EUV

One thing I have contemplated about the EUV timeline is that while we can easily argue that the leading edge IDM's such as Intel and Toshiba/Samsung may well have already raced paced the easy-ground for EUV by way of litho tricks and magic with their immersion tools and computational lithography (tricks that can obviously be put to work with EUV as well, extending EUV's own viability too)

Computational yes, but you can't have immersion EUV, given that EUV is done in vacuum, and that water isn't transparent to EUV.

 

[bryanW1995]

I was just finishing this thead when the forums went down this morning. I almost thought that Khon's link was so technical that it blew up the forums!!