Intel Cans Tejas...End of Netburst???

[sao123]

XbitLabs is reporting Prescott as the end of Netburst Architecture with Tejas project canned.
Read Article here...
XbitLabs.com -> Intel to Cancel NetBurst, Pentium 4, Xeon Evolution:Tejas, Jayhawk Reportedly Shelved

So what made netburst so superiour to the P3 Dynamic Execution Micro-Architecture? Aside from the fact it seemed to be a brute force architecture benefitting only from raw speed and a little optimization.

Now it seems we may be heading to Pentium M architecture (which i am not familiar with) but I've heard it is based back on the p3 architecture. How has the P3 architecture improved so much to allow this new development? Will this new architecute incorporate some of the benefits from netburst such as hyprethreading, quad pumping, dual channeling, etc?

Tejas was supposed to be intels golden child, the one who beats AMD...now its a dissolved dream...How will these next generation chips fare against an already highly competitive AMD chips which seem to now have the upperhand. Can a low power laptop cpu really compete with a highend desktop cpu?

I have concerns for intel now.

 

[LeftSide]

Well to answer your question the PentiumM is just a suped up P3. Its basicaly the P3 core with a 400mhz front side bus. It also has the multimedia extensions (sse1 and sse2, *sse3 on next gen*)and energy saving functions. It also has 1meg of L2 cache (2megs on the next core) and supports the p4 netburst architecture. They probably will encorperating Hyper-threading for media resons, but it wont give as much of a perfomance boost as the p4. This is because the P3 has a 15 stage pipeline instead of the p4's 20 (or 30 for presscot).

Edit: Read page 8
That should give you all the info you need.

Oh and I think they are going to make the Pentium M into a dual core. Things are starting to get interesting...

 

[zephyrprime]

The p3 only has 10 stages. I don't know about the P-M.

 

[LeftSide]

P3 has 10? must have gotten it confused with the Athlon.... I thought I read somewhere that the Pentium M had 15. I'll have to double check

 

[Sahakiel]

I thought Athlon had 10 stages and Pentium 3 had 12 or 14

 

[SuperTool]

Very simple, IMO. The double pumping of integer unit was unsustainable. Intel is not getting much return for that investment. They don't advertize that their integer units are double pumped, and they could get the same performance and area with lower power by just replicating these pipes. It has gotten worse with Prescott, because their previous design could not keep up with the core frequency increase, so they replaced it with a new Low Voltage Swing technology. http://developer.intel.com/technology/itj/2004/volume08issue01/art04_lvs_technology/p01_abstract.htm
This technology is an engineering marvel, but from what I am hearing, it takes several times as many engineers to design and verify something with it, and it burns power like crazy because of the differential sensing, which is why the Prescott is so hot. It's basically getting to the point where they are hitting a wall with diminishing returns, where they are throwing armies of engineers just to be able to have the integer unit at 2x speed of the CPU. It's hard enough designing dynamic pipelines, but when you make them differential mode low swing, you have a lot less margin for error, and it gets a lot trickier. Also, I am sure the power densities were going through the roof already.

 

[CTho9305]

I thought it only double pumped 16 bit operations.

edit: that LVS logic looks sort of like a cascode circuit.... in a cascode the cross-coupled pmos devices act kinda like a sense amp.
edit2: wow, that's pretty cool stuff.

 

[SuperTool]

Here is an interesting sentence.

And even after pruning the number of timing paths using patented algorithms [4], the rotator alone required simulations on more than 60,000 paths to characterize the circuit.