I mean, it's on the borderline of "feasible" with the 10 core CML. Either they have to use denser libraries, or.... did just Intel suddenly start to think that producing MUCH larger dice for roughly the same price, thus further reducing profit margin is OK? That really didn't seem their way of thinking so far. I'm not trying to be funny or rude here, I just think that both moves are bad.
I'm 1000% sure there were engineers who told the management very early on to scrap 10nm and pull forward a much less agressive 7nm (not _that_ dense and withouht EUV for the first iteration). I don't think it could have been any harder, any more time consuming and more importantly, financially much more forgiving than spending years and countless billions to fix a fundamentally broken process.
At this point, nobody could convince me that ICL sales covered more than 1-2% of what 10nm """development""" cost so far. As for ICL servers? Starting to turn into a Cannon Lake gig.
Hence the talk about them using chiplets. But we'll see if that actually ends up happening.
Edrick
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Ajay
Lifer
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And those engineers would have been wrong. Not having EUV is part of the reason that 10nm was so borked in the first place. Intel process engineers threw the kitchen sink at 10nm trying to get the density they wanted. So much for that approach. Still, Intel had to push through 10nm on the way to 7 anyway, once committed, they had to learn from their mistakes so as not to repeat them on 7nm. Sorta the same situation when TSMC put out 20nm, even though it was pretty rough and had few big design wins.
DrMrLordX
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Intel swears up and down we'll see them. After all the delays, I'm not sure they'll matter much. Intel is doing a good job of selling more Cascade Lake.
uzzi38
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Supposedly when some OEM gets supply of Tiger Lake.
In other words, this is probably when it ships to OEMs. The OEM in question seems to be a major one if they're using Lakefield (as not many are).
Timing makes sense. The initial run of Tiger Lake is likely to be only a few models, Oct/Nov seems about right for the full release.
Richie Rich
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Chiplet design is great for heavy multicore applications... like servers. This is the main market I'd expect it from Intel at 1st place. Alder Lake is kind of surprasing however it can be just side effect similar to what AMD did. Low-leak efficient dies goes to server and high-leak high-clock dies and partly disabled goes to desktop. If chiplet design brings huge benefits, and it does, than soon or later Intel will adopt that too.
However there is many ways how Intel can screw this up. I can imagine they can try to go next-gen with EMIB or interposer and easily end up in development delay hell. But implementation of 1st gen Zen2 chiplet design should be easy for Alder Lake.
Definitely is destined to be like Cooper in that it only ends up shipping to a few customers at best.
Note that in the earlier roadmaps Sapphire Rapids was meant to be released in the middle of 2020 and then later Q1 2021. That's obviously not going to happen but unlike the Whitley chips it's more likely to get an actual release
Ajay
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They'll make one someone an offer they can't refuse. Presto, revenue of the books. Investors satisfied that Intel delivered on promise, just so long as the money train keeps rolling.
DrMrLordX
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Interesting information about ADL-S and the LGA1700 platform.
Looks like ADL-S will have both big+little cores as previously leaked, using the Golden Cove and Gracemont (with AVX512 support!!) cores.
Looks like ADL-S will have both big+little cores as previously leaked, using the Golden Cove and Gracemont (with AVX512 support!!) cores.
coercitiv
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A rumor that starts with "Intel long-life platform"? No thanks.
Intel changes socket pins more often than Cloudflare changes CPU providers.
Intel changes socket pins more often than Cloudflare changes CPU providers.
uzzi38
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PCIe Gen 5 isn't coming to consumers to soon, and certainly not before DDR5 support. Far too costly.
Smells like BS. I have major reservations about this one.
The small cores are for mobile, but S is going to be along for the ride. It does allow marketing to say the top model has 16 cores.
So something like:
i9: 8+8
i7: 8+4
i5: 6+0
i3: 4+0
I guess it makes sense to add AVX512 to Gracemont for ISA compatibility, but I doubt it will be fast AVX512.
IntelUser2000
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- Oct 14, 2003
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There's nothing preventing Intel making an enthusiast chip well over 200mm2. Intel's first generation Core i7 had a die size of 263mm2.
Sure the modern processes have higher costs overall, but so are the prices. Sandy Bridge sold for $300 on the top tier with a 215mm2 die. The top AMD/Intel CPUs sell for $500. That's way, way beyond inflation and they are benefitting handsomely from what little manufacturing cost increase there is.
Don't think Intel/AMD/Nvidia are being nice to you and absorbing all the pains of increased costs, because they are more than making up for it with price increases. They market every year how impressive the technology is basically conditioning people that the higher prices are justified. It may or may not be justified, but they are making business decisions that absolutely does not incur losses for the company.
If they go the route of using MCM for Alderlake I assume it'll only be the IMC/PCI Express/Graphics that are on the seperate chip. Richie's assumption that Gracemont and Golden Cove will be seperated are completely ridiculous, because you lose any point of doing such a configuration.
Sure the modern processes have higher costs overall, but so are the prices. Sandy Bridge sold for $300 on the top tier with a 215mm2 die. The top AMD/Intel CPUs sell for $500. That's way, way beyond inflation and they are benefitting handsomely from what little manufacturing cost increase there is.
Don't think Intel/AMD/Nvidia are being nice to you and absorbing all the pains of increased costs, because they are more than making up for it with price increases. They market every year how impressive the technology is basically conditioning people that the higher prices are justified. It may or may not be justified, but they are making business decisions that absolutely does not incur losses for the company.
If they go the route of using MCM for Alderlake I assume it'll only be the IMC/PCI Express/Graphics that are on the seperate chip. Richie's assumption that Gracemont and Golden Cove will be seperated are completely ridiculous, because you lose any point of doing such a configuration.
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I'm not sure what to make of that rumor. I can believe Alder Lake is big.LITTLE, but the rest just seems kinda off. By 2021-2022, one would hope DDR5 support is a given, so why is he even questioning it. PCIe 5.0 support should also be somewhat likely, if not for Alder Lake, then at least Meteor Lake timeline.
Also, skeptical of AVX-512 on Gracemont. AVX2 I can definitely see, but if AVX-512 support exists, it would definitely have to be through microcode only.
I think they'll be quicker to cut the big cores than Atom cores. So something more like:
i9: 8+8
i7: 6+8
i5: 6+0
Maybe a 4+8 and 2+8 in there somewhere? Certainly complicates the lineup.
Tremont cores are about 1/4th the size of Sunny Cove. If Gracemont and Golden Gove maintain that ratio, then it's easy to see why an 8 core Atom die would be pointless. Would be so tiny that the overhead wouldn't justify its existence. Far better to just have a single 8+8 die.
As for disaggregation, I think the most logical component to separate out first would be the GPU. They'd want the memory controller to be on the CPU/SoC die for latency reasons. Or they could go with an AMD-style IO die and a separate die for the cores. Lots of ways to split it up.
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IntelUser2000
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@Exist50 It's precisely because of the iGPU's latency and bandwidth requirements that Arrandale/Clarkdale opted for GMCH as a separate chiplet. If anything modern iGPUs are even more sensitive, not less. Sure you will lose some CPU performance compared to a monolithic setup which is why chiplets are a compromise, not a magic bullet like some believe.
Intel chips might be affected more due to the better performing memory controller, but overall Ryzen 3000 does pretty well overall on the CPU side despite the separate die memory controller.
The support is likely going to be similar to how AMD's Jaguar worked with AVX. So it'll take several cycles to execute one AVX-512 instruction. AVX-512 support is mandatory for the "little" cores unless they want to disable it again on Golden Cove cores like they did with Lakefield.
Asynchronous support where one set of cores support AVX and one doesn't isn't going to work out for the Windows ecosystem. Moving to a hetereogenous setup is already a big deal even if the ISA parity exists.
I agree with this too. But the leak showed 8+8+1 125W, 8+8+1 80W, and 6+0+1 80W.
Intel chips might be affected more due to the better performing memory controller, but overall Ryzen 3000 does pretty well overall on the CPU side despite the separate die memory controller.
The support is likely going to be similar to how AMD's Jaguar worked with AVX. So it'll take several cycles to execute one AVX-512 instruction. AVX-512 support is mandatory for the "little" cores unless they want to disable it again on Golden Cove cores like they did with Lakefield.
Asynchronous support where one set of cores support AVX and one doesn't isn't going to work out for the Windows ecosystem. Moving to a hetereogenous setup is already a big deal even if the ISA parity exists.
I agree with this too. But the leak showed 8+8+1 125W, 8+8+1 80W, and 6+0+1 80W.
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IntelUser2000
Elite Member
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There's a full slide of it at Notebookcheck.
It's actually when it ships to Lenovo. Cometlake U and Renoir are shown as early May and mid May respectively. Obviously Cometlake U was available much earlier so this doesn't necessarily mean Tigerlake is coming at that time.
AFAIK Icelake isn't used at all in their Thinkpad lineups so for Tigerlake generation more 10nm products are used by Lenovo. This may also have something to do with the fact that Icelake doesn't have a business oriented version at all.
I'd still lean on Lisa Pearce saying that it'll ship to OEMs summer.
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