uzzi38
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- Oct 16, 2019
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Those are kind of the biggest problem at hand with the idea of a Willow Cove backport though. The cores and analog logic surrounding it are precisely the issue. Though, to be fair, regardless of what Rocket Lake is it does appear some of that analog logic is being brought back - iirc Sharkbay did talk about IMVP9 for Rocket Lake, which has only been a thing for the Cove products thus far. Skylake and it's derivatives used IMVP8, but as for the cores on top of that I'm not sold.The exceptions are "hard IPs" like Intel's current cores and analog logic like PHYs, FIVR, etc. These are not synthesizable, and tied directly to the process. These too can be backported, but there's significantly more effort involved, and in the worst case it can resemble most of a redesign than a port. Still not impossible, however, if you're willing to throw the time, and manpower into it.
In any case, time is still a bit of an issue if they started in 2019.
Not much else I can say except those were the numbers they gave as part of their own estimations. They definitely felt it would become a serious problem in the 4+GHz range anyway. Though at this point they were definitely thinking of all-core frequencies looking back at it - not ST. Which, to be fair, is a bit on me for misreading.There would be a power penalty, surely, but again, this greatly exaggerates it. It's no secret that Cdyn scaling between nodes has slowed in recent years, and that is particularly apparent for 10nm. I imagine the penalty would be in the ballpark of 25% more power (roughly in line with the core difference between Rocket Lake and Comet Lake), not something obscene like 100%.