Discussion Intel current and future Lakes & Rapids thread

[Adonisds]

It's more like . . . if Intel had a competitive product, AMD's prices couldn't creep upwards like that.



What's with the 398 MHz clocks? No wonder the scores are so low.



Short-term thinking is endemic in American board rooms. There's probably other, more-specific reasons. But for now, Intel has to save face and keep up that stock price.

The Intel stock has outperformed SP500 in the last 5 years, and that's when they lost their ample manufacturing lead.

I understand that there's a lot more to an Intel stock analysis than the 10nm situation, it's a very complex analysis. Anyone here wants to try to explain why the stock had a very good performance in the last 5 years?

 

[Ajay]

The Intel stock has outperformed SP500 in the last 5 years, and that's when they lost their ample manufacturing lead.

I understand that there's a lot more to an Intel stock analysis than the 10nm situation, it's a very complex analysis. Anyone here wants to try to explain why the stock had a very good performance in the last 5 years?

Share buybacks.

 

[ondma]

Why do they care about their stock prices enough to do these 10nm paper launches? Even assuming they have to care, wouldn't paper launches only help the stock prices in the short term, and hurt in the medium term because it's highly inefficient and results in losses building 10nm chips with terrible yields and then having to bribe OEMs to launch them?

If the product is available (and Icelake notebooks certainly are) it by definition is not a "paper launch". And if you have any proof of those "bribes", perhaps you could like you know.... produce it, instead of spreading unsubstantiated accusations.

 

[maddie]

Share buybacks.

Probably more like stock options.

 

[Markfw]

If the product is available (and Icelake notebooks certainly are) it by definition is not a "paper launch". And if you have any proof of those "bribes", perhaps you could like you know.... produce it, instead of spreading unsubstantiated accusations.

I would say thats a logical deduction, since they are not great, they are not fast, and not priced that great.

The paper launch is about the fact that only a small number of laptop chips are out, no desktop, and not in quantity for laptops.

 

[jpiniero]

The paper launch is about the fact that only a small number of laptop chips are out, no desktop, and not in quantity for laptops.

The availability is better than I thought but the quality of the chips is pretty crappy. They are no doubt binning very loosely. Sunny Cove being a decent upgrade from Skylake makes it work though.

 

[Ajay]

Probably more like stock options.

No, actually buying back stock from investors. Here's an example from 2018 where Intel added $15B US to it's repurchase program - 15 BILLION!

Intel Adds $15 Billion to Buyback Program | The Motley Fool

The company's prior repurchase authorization was running out.

www.fool.com

 

[Adonisds]

If the product is available (and Icelake notebooks certainly are) it by definition is not a "paper launch". And if you have any proof of those "bribes", perhaps you could like you know.... produce it, instead of spreading unsubstantiated accusations.

I should have worded that better. I was referring mainly to the cannon lake launch last year. There's certainly no proof that OEMs were "bribed" to make them, but it's plausible. Many were talking about that, such as: https://www.semiaccurate.com/2018/05/29/is-intels-upcoming-10nm-launch-real-or-a-pr-stunt/

But that's not the point. The point is that doing those things doesn't seem like the most efficient plan, unless you need to deliver a marketing message and keep the stock price high

 

[maddie]

No, actually buying back stock from investors. Here's an example from 2018 where Intel added $15B US to it's repurchase program - 15 BILLION!

Intel Adds $15 Billion to Buyback Program | The Motley Fool

The company's prior repurchase authorization was running out.

www.fool.com

Then why would you want a higher price before buying? I understand repurchases to keep it high, but in this case they appear to be stoking it up in a different manner.

 

[trivik12]

No, actually buying back stock from investors. Here's an example from 2018 where Intel added $15B US to it's repurchase program - 15 BILLION!

Intel Adds $15 Billion to Buyback Program | The Motley Fool

The company's prior repurchase authorization was running out.

www.fool.com

Almost every profitable company is doing it. Even Apple has had a huge stock buyback. Its driven by huge reduction in corporate tax rate and also extremely low interest rates. Currently Intel's dividend is higher than 10 year treasuries !!!!

That said their Top like has grown from 55B in 2015 to 71B? in 2019. That is non trivial considering so many markets are are not growing or even shrinking(especially desktops and laptops).

 

[tamz_msc]

That Tiger Lake-Y Geekbench 5 result detects an interesting cache configuration - 1.25 MB L2/core and 12 MB L3.

 

[Cardyak]

That Tiger Lake-Y Geekbench 5 result detects an interesting cache configuration - 1.25 MB L2/core and 12 MB L3.

1.25MB of L2 Cache per Core sounds enormous compared to what we're used to. Sunny Cove only has 512KB, and earlier generations only 256KB.

Could be a misreading of course, but if this is a legitimate L2 reading then it could be a big step up in caching.

 

[JoeRambo]

That Tiger Lake-Y Geekbench 5 result detects an interesting cache configuration - 1.25 MB L2/core and 12 MB L3.

Yeah, that is the most interesting part of that leak. 48kb L1 Data / 32kb L1 Instruction + 1.25MB of L2/Core and 3MB of L3 per core is interesting cache hierarchy.

Old client CPUs had 256kb of L2 inclusive in 2 or 1.5 MB L3 per core, so what was remaining was ~1.25-1.75 or so of L3 cache per core, making inclusive scheme work fine.
This new configuration of 1.25MB of L2, could again be inclusive in 3MB of L3, leaving ~1.75MB of L3. Major difference from server Skylake, where 1MB of L2 was impossible to back with tiny L3 per core and Intel had to abandon inclusive L3 cache.

 

[IntelUser2000]

Actually two results have been published so far.

Given linear scaling the results at 3.9GHz would be impressive 1423 GB5 points which is nothing to sneeze at since it's most likely preproduction silicone. 1065G7 running at 3.9GHz reaches ~1325 points. Multicore results can't be multiplied the same way of course due to thermal constraints.

~7% gains, but Geekbench 5 scales linearly just like Geekbench 4, again making it not realistic.

That Tiger Lake-Y Geekbench 5 result detects an interesting cache configuration - 1.25 MB L2/core and 12 MB L3.

Intel said Willow Cove has its cache redesignd, not cache increased. The weird number is interesting because it does suggest a big redesign.

One possibility is they are splitting the L2 cache into instruction and data with bigger portion being the instruction. To keep the worst case data cache size not decrease, it would be 768KB Instruction L2 + 512KB Data L2.

 

[Zucker2k]

~7% gains, but Geekbench 5 scales linearly just like Geekbench 4, again making it not realistic.

But this is far from optimal performance especially if one considers what must be terrible memory speed/latency at those clocks.

 

[JoeRambo]

One possibility is they are splitting the L2 cache into instruction and data with bigger portion being the instruction. To keep the worst case data cache size not decrease, it would be 768KB Instruction L2 + 512KB Data L2.

That would be nonsense changes IMHO. Separate L2 instruction cache achieves nothing, I think instruction caches are shining examples of locality and "sequential" execution, so simply having unified L2 takes care of instruction caching needs and prefetches perfectly fine?

There is nothing keeping Intel from using whatever L2 size they fancy. Sure it is a function of latency and diminishing hit rate returns etc, but 512kb, 1024kb, 1280kb are all valid sizes for L2, I feel 1024 and 1280 are in same ballpark of design constraints. The real question is whether L3 is inclusive ( indicating "ring" style design ), or is it eviction cache ( with prefetch secret sauce whatever ), making it similar to server Skylake designs.

My bet is on inclusive L3, as that would make working with chiplets and integration much easier - L3 serves as "home agent" for cache lines inside all cores and in L3 cache.

 

[mikk]

Intel said Willow Cove has its cache redesignd, not cache increased. The weird number is interesting because it does suggest a big redesign.

A cache redesign won't automatically rule out cache increases, more the other way around. As for L3 size we have confirmations from several sources that Willow Cove gets a bigger size, so your Intel didn't say cache increase point is invalid on this matter.

 

[jpiniero]

I'm assuming that Geekbench is simply misdiagnosing the L2 and it is 256 KB L2 (down from 512 KB in Sunny Cove) and 3 MB L3 per core.

 

[coercitiv]

Intel said Willow Cove has its cache redesignd, not cache increased. The weird number is interesting because it does suggest a big redesign.

A cache redesign won't automatically rule out cache increases, more the other way around. As for L3 size we have confirmations from several sources that Willow Cove gets a bigger size, so your Intel didn't say cache increase point is invalid on this matter.

The quoting system failed a bit so I'm connecting the reply to it's original source.

 

[Adonisds]

Why does Intel still plans to name their future processes so that their "x nm" are much denser than all the others?

Even after people have been saying for years that the name of the processes means nothing and that Intel's are always much denser, all the time I see people assuming that they do and that Intel is in a much worse situation compared to the other fabs than it in fact is just because of that. And I'm not talking about only websites for tech enthusiasts.

Intel cares a lot about and spends a lot on marketing. All that effort on the cannon lake launch was about marketing. Isn't the wise marketing move to just call their 7nm process 3nm, 2nm, whatever is more appropriate?

 

[mikk]

I'm assuming that Geekbench is simply misdiagnosing the L2 and it is 256 KB L2 (down from 512 KB in Sunny Cove) and 3 MB L3 per core.

There is no evidence. Geekbench is usually accurate when it comes to the cache size.

 

[Dayman1225]

Looks like Intel's integrated thunderbolt controller on the Icelake SoC really helps with eGPUs - upto 30% performace gains versus an 8750H

 

[jpiniero]

https://twitter.com/x/status/1200042853587537921

Rocket Lake might be 8 cores max on desktop. Also Tigerlake indeed does support LPDDR5 at speeds of 5400 although U is 28W?

 

[uzzi38]

https://twitter.com/x/status/1200042853587537921

Rocket Lake might be 8 cores max on desktop. Also Tigerlake indeed does support LPDDR5 at speeds of 5400 although U is 28W?

28W is a maximum.

Same with CML-H. 65W is a maximum.

Also the LPDDR5 rumour is from Sharkbay as well, you're confirming his leak with his own info

Either way, there's a solid chance his (still) right.

 

[jpiniero]

Either way, there's a solid chance his (still) right.

True. He goes on to say that he doesn't think there will be an Rocket Lake i9 although perhaps from another platform (Sapphire Rapids?)