Discussion Intel current and future Lakes & Rapids thread

[Zucker2k]

Because the "+" defines an improvement over a node that works. If the vanilla 10nm node is not be spoken of, then by definition 10+ is actually 10, more exactly their first 10nm working node.

The Cannon Lake based CPU needs to be searched by SKU id on Intel's CPU database, it's not listed in the 8th gen CPU list, nor is there a Cannon Lake page on Intel's site as all other codenames have. It's only purpose was to enable Intel claim their 10nm node was working, and it failed at that as well.

I think you answered your own question then?

I was genuinely expressing doubt Intel would be using 10 NOW when it's clear they've moved to 10+, but I suppose you were aiming at triggering responses about the failure of vanilla 10nm.

 

[IntelUser2000]

Possible that Lakefield, Snowridge and NNP-I is on regular 10nm.

I supposed though arguing about what cores are on what + nodes are really insignificant when considering nothing is truly a simple process shrink nowadays. Nvidia when talking about Pascal, mentioned circuit changes to reach high clock speeds(despite moving to 16/14nm). This is in stark contrast to the old days of scaling when a straight shrink basically guaranteed higher clocks or lower power, or a combination of both.

I also don't think we'll see 5GHz stock CPUs until maybe tail end of 7nm(7nm++), and Coffeelake is an outlier. It's just a result of squeezing every last drop out of 14nm than 14nm being inherently superior.

 

[coercitiv]

but I suppose you were aiming at triggering responses about the failure of vanilla 10nm.

Actually no, and it was @Dayman1225 who provided a list of other chips that may still use vanilla 10nm. But I suppose you're not really interested in the messy details of Intel's roadmaps, are you?

Next time you accuse me of something try to be more subtle, or correct.

I also don't think we'll see 5GHz stock CPUs until maybe tail end of 7nm(7nm++), and Coffeelake is an outlier. It's just a result of squeezing every last drop out of 14nm than 14nm being inherently superior.

We're still getting the hefty benefit of lower operating voltage, so as long as we keep the same number of cores we will see increased sustained speeds in previously TDP constrained scenarios. Meanwhile workloads that really benefit from high ST performance typically use a fraction of the real power in these chips, meaning they'll be able to maintain high clocks anyway, localized heat will be less of a problem. The only people who will really feel the secondary effects of feature shrinkage in the form of extreme heat and fmax drop will be overclockers running MT AVX loads.

But hey, maybe Coffee Lake Refresh will be the Sandy Bridge of this decade...

 

[DrMrLordX]

I was genuinely expressing doubt Intel would be using 10 NOW when it's clear they've moved to 10+,

There isn't much evidence that Intel has moved on to 10nm+. IceLake-U/Y still won't have more than 4c mobile parts. Yields are likely to be low. Availability of chips will likely be low. There's no telling how (or if) Intel will really push IceLake-SP onto the market with any kind of presence despite their claims of sampling and numerous systems "powered on". Those statements don't pass the sniff test. If that's the fruit of 10nm+ then ugh.

 

[IntelUser2000]

But hey, maybe Coffee Lake Refresh will be the Sandy Bridge of this decade...

Really?

Coffeelake is a result of an unfortunate, and numerous rehashing of Skylake. It's got to go. AMD 7nm Ryzen will be another big jump. 10 core Comet Lake will look extremely deficient. On server Intel will probably be pretty close in performance with Cooper Lake, but coming 6+ months after and at 350W versus 250W for Rome.

 

[coercitiv]

Really?

Coffeelake is a result of an unfortunate, and numerous rehashing of Skylake. It's got to go. AMD 7nm Ryzen will be another big jump. 10 core Comet Lake will look extremely deficient. On server Intel will probably be pretty close in performance with Cooper Lake, but coming 6+ months after and at 350W versus 250W for Rome.

I thought we were talking about fmax potential and frequency ceiling of 10n / 7nm, not whether the architecture needs improvement or not.

 

[jpiniero]

https://ranker.sisoftware.co.uk/sho...e9d8fe97aa8ce4d9ff87ba9cf99ca191b7c4f9c1&l=en

Another Icelake sighting, this time of the i5 1035G1. So maybe that leaked list was legit...

Edit: And here's one of the i5 1035G4.

https://ranker.sisoftware.co.uk/sho...d5e2d5edd5e2d5f381bc8caacfaa97a781f2cff7&l=en

 

[Dayman1225]

https://ranker.sisoftware.co.uk/sho...e9d8fe97aa8ce4d9ff87ba9cf99ca191b7c4f9c1&l=en

Another Icelake sighting, this time of the i5 1035G1. So maybe that leaked list was legit...

Edit: And here's one of the i5 1035G4.

https://ranker.sisoftware.co.uk/sho...d5e2d5edd5e2d5f381bc8caacfaa97a781f2cff7&l=en

Those names... Jesus

 

[jpiniero]

Those names... Jesus

The Comet Lake names are worse TBH.

Will say that Icelake is going to be a hard sell compared to Comet Lake, assuming those clocks are mostly accurate. Which may be just fine for Intel given the yields.

 

[scannall]

The Comet Lake names are worse TBH.

Will say that Icelake is going to be a hard sell compared to Comet Lake, assuming those clocks are mostly accurate. Which may be just fine for Intel given the yields.

How many generations of 14nm until they use the name 'Dry Lake'?

 

[TheGiant]

imo they should call it the pluslake

 

[jpiniero]

How many generations of 14nm until they use the name 'Dry Lake'?

Rocket Lake is probably it for 14 nm. Maybe. If 7 nm flops and they really don't have a backup plan at a foundry node that actually works, I could see a minor refresh of Rocket Lake at the end of 22 just to have something new.

 

[Dayman1225]

A Tigerlake 2 core ES has appeared on Sisoft, nothing really interesting to take away from it.

1.8GHz clock, L2 is 256KB per core which is a bit odd, perhaps a misreading since Icelake is 512.

 

[Ajay]

Rocket Lake is probably it for 14 nm. Maybe. If 7 nm flops and they really don't have a backup plan at a foundry node that actually works, I could see a minor refresh of Rocket Lake at the end of 22 just to have something new.

Intel would need to make a foundry commitment now in order to have the capacity available in 2021 - and even then it wouldn’t be close to the wafer output they need. If Intel 7nm EUV doesn’t hit HVM in 2021-2022, the x86 market will be in chaos - TSMC won’t be able to meet demand for Zen products and prices will start skyrocketing. Intel will be the cheaper, more widely available supplier of late generation products. That would be some serious Irony. FWIW, I seriously doubt this will happen, but if someone told me 3 years ago that 10 nm would be borked in 2019 - I would have laughed in their face.

 

[tamz_msc]

A Tigerlake 2 core ES has appeared on Sisoft, nothing really interesting to take away from it.

1.8GHz clock, L2 is 256KB per core which is a bit odd, perhaps a misreading since Icelake is 512.

Intel says amount of cache would vary by product segment for Ice Lake. It isn't a misreading. Besides Willow Cove is supposed to have redesigned cache.

 

[jpiniero]

Intel says amount of cache would vary by product segment for Ice Lake. It isn't a misreading. Besides Willow Cove is supposed to have redesigned cache.

I was thinking it could be Rocket Lake since it would likely be using the Tiger Lake platform.

 

[ajc9988]

10nm has some really aggressive UHP (Ultra High Power i presume) cell libraries, that sacrifice way more densitiy than 14nm++ (vs 14nm HD):

It remains to be seen when Intel finally manages to ship silicon using that process. If they do however, it should clock quite decently. The main question is of course when will that be?
If I had to guess, I'd say, probably a year after the mobile Ice Lake releases (if no additional issues crop up)- Considering that Intel actually seems to ramp up 10nm now. $530M dollar loss for ramp-up at least means they are somewhat more serious of actually delivering something by the year-end.

This is a repost of my analysis on why Intel's purported density means NOTHING in discussion of actually implemented density on chips:

Post 1 -
https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html

Post 2 -

So, I thought at first that the 66MTr/mm2 was from the estimated density for the Apple A12, which was floated around the time of its release. I was wrong. Here is the information to analyze density comparisons for process nodes to put them into context:

This is the list on approximate transistor densities with some information on context. (full source: https://www.techcenturion.com/7nm-10nm-14nm-fabrication ).

As you can see, when you compare Intel's SRAM numbers, the only one provided, to TSMC's HPC process, that is where the comparing 100.8 to 66.7MTr/mm2 comes from. But take notice that TSMC's low power process for mobile chips is at 96.5MTr/mm2.

Now, let us examine an Anandtech chart looking at actual densities in final silicon:

https://www.anandtech.com/show/13687/qualcomm-snapdragon-8cx-wafer-on-7nm

Notice that for the companies that used the TSMC 7nm FF/FF+ node, Qualcomm reached to up to 94.6MTr/mm2, the HiSilicon Kirin reached 93.1MTr/mm2, and the Apple A12 Bionic reached 82.9MTr/mm2. Those are 98%, 96.5%, and 86%, respectively, of the theorized transistor density. That is pretty good.

But let's examine what happens when we look at Intel's 14nm process, with the theoretical density of 43.5MTr/mm2. Intel, with Skylake 4+2 achieved just 14.3MTr/mm2, or a 33% density compared to the theoretical value that Intel published.

Let's look at AMD's results. Using Samsung/GF 14nm process with a theoretical transistor density off 32.5MTr/mm2, they achieved an actual density of 25MTr/mm2, or 77% of the theorized density. That is pretty good.

So, assuming that the achieved density versus theoretical will be approximately the same, while AMD is using the HPC TSMC process rather than the more dense low power variant, you would take the 66.7MTr/mm2 * 0.77 (77%), which equals 51.3MTr/mm2.

Now it is time for Intel. So, taking the theoretical 100.8MTr/mm2 * 0.33 (33%), you get 33.3MTr/mm2, or roughly 18MTR/mm2 less dense than AMD.

Now, one reason to do less density is heat. By making it less dense, the neighboring transistors contribute less so that the heat density is lower which can allow for higher frequencies at the same temp as a denser chip with lower frequencies. This is part of where Intel gets their high frequency. But, with that, you also wind up with fewer transistors to contribute to doing the work. So, there is a theoretical IPC trade-off. This also isn't comparing the final transistor count nor the die area, although those are provided in the table above. When doing that, you can see why I am very impressed with Intel's engineers ability to design microarchitecture. They have great performance with about 60% of the density of a Ryzen chip, while achieving 25% more frequency, with the rest coming from IPC due to architectural design.

One should always show respect for achievements. AMD deserves respect for achieving the density that they have, Intel on microarchitecture. But to look at densities in a vacuum, especially theorized on SRAM instead of actual results achieved, is more than misleading.

 

[jur]

This is very strange. Intel's transistor counts may be a bit off. 8 core Coffee Lake measures ~175 mm^2 and it also includes gpu. Ryzen at 192 mm^2 has no gpu. Coffee Lake has generally higher ipc, clocks better and also has native avx2. So either amd produced subpar design, requiring a lot more transistors and more cache to achieve similar ipc, or Intel's transistor count is simply not accurate. I think the latter is more probable.

 

[TheGiant]

no it is accurate

the implementation is that defines tr count IMO

above in higher posts is the process capability

but as you said it doesnt matter, in fact to achieve that performance with that clock with that TR count, really /bow to Intel engineers

anyone has some estimate about icelake 4+2 with that 64EUs? size, tr count? care to share?

 

[Dayman1225]

This is a repost of my analysis on why Intel's purported density means NOTHING in discussion of actually implemented density on chips:

Post 1 -
https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html
View attachment 6454
Post 2 -

So, I thought at first that the 66MTr/mm2 was from the estimated density for the Apple A12, which was floated around the time of its release. I was wrong. Here is the information to analyze density comparisons for process nodes to put them into context:

This is the list on approximate transistor densities with some information on context. (full source: https://www.techcenturion.com/7nm-10nm-14nm-fabrication ).

As you can see, when you compare Intel's SRAM numbers, the only one provided, to TSMC's HPC process, that is where the comparing 100.8 to 66.7MTr/mm2 comes from. But take notice that TSMC's low power process for mobile chips is at 96.5MTr/mm2.

Now, let us examine an Anandtech chart looking at actual densities in final silicon:

https://www.anandtech.com/show/13687/qualcomm-snapdragon-8cx-wafer-on-7nm

Notice that for the companies that used the TSMC 7nm FF/FF+ node, Qualcomm reached to up to 94.6MTr/mm2, the HiSilicon Kirin reached 93.1MTr/mm2, and the Apple A12 Bionic reached 82.9MTr/mm2. Those are 98%, 96.5%, and 86%, respectively, of the theorized transistor density. That is pretty good.

But let's examine what happens when we look at Intel's 14nm process, with the theoretical density of 43.5MTr/mm2. Intel, with Skylake 4+2 achieved just 14.3MTr/mm2, or a 33% density compared to the theoretical value that Intel published.

Let's look at AMD's results. Using Samsung/GF 14nm process with a theoretical transistor density off 32.5MTr/mm2, they achieved an actual density of 25MTr/mm2, or 77% of the theorized density. That is pretty good.

So, assuming that the achieved density versus theoretical will be approximately the same, while AMD is using the HPC TSMC process rather than the more dense low power variant, you would take the 66.7MTr/mm2 * 0.77 (77%), which equals 51.3MTr/mm2.

Now it is time for Intel. So, taking the theoretical 100.8MTr/mm2 * 0.33 (33%), you get 33.3MTr/mm2, or roughly 18MTR/mm2 less dense than AMD.

Now, one reason to do less density is heat. By making it less dense, the neighboring transistors contribute less so that the heat density is lower which can allow for higher frequencies at the same temp as a denser chip with lower frequencies. This is part of where Intel gets their high frequency. But, with that, you also wind up with fewer transistors to contribute to doing the work. So, there is a theoretical IPC trade-off. This also isn't comparing the final transistor count nor the die area, although those are provided in the table above. When doing that, you can see why I am very impressed with Intel's engineers ability to design microarchitecture. They have great performance with about 60% of the density of a Ryzen chip, while achieving 25% more frequency, with the rest coming from IPC due to architectural design.

One should always show respect for achievements. AMD deserves respect for achieving the density that they have, Intel on microarchitecture. But to look at densities in a vacuum, especially theorized on SRAM instead of actual results achieved, is more than misleading.

This is all good stuff, but it’s not to say that Intel cannot ship close to theoretical 14nm Density chips, for example; Intel Loihi is 34.5MTr/mm^2 and Stratix 10 FPGA is 30~MTr/mm^2

 

[ajc9988]

This is all good stuff, but it’s not to say that Intel cannot ship close to theoretical 14nm Density chips, for example; Intel Loihi is 34.5MTr/mm^2 and Stratix 10 FPGA is 30~MTr/mm^2

Actually, it says exactly that. Once you change to the HPC libraries on Intel's process, you are not getting anywhere near that 100.8MTr/mm2. It's impossible. Just like going to TSMC HPC node reduces the density from the mid 90s to 66MTr/mm2. That means Intel CAN NOT hit that density on their desktop and Xeon offerings.

Edit: Now that I have woken up more and am having a cup of coffee, let's examine the theoretical max of Intel 14nm vs your two examples and look at Xeon density.

The theoretical maximum is 43.5MTr/mm^2. The two examples you gave, which likely do not include the HPC libraries, are 34.5 and 30. That is 79.3% and 69%, respectively, the maximum theoretical density published by Intel. If those were built on the 14nm++ process, with a theoretical max of 37.22MTr/mm^2, then they reach 92.7% and 80.6%, respectively, while noting that the "+" variants reduce the maximum theoretical density.. That is on a neuromorphic chip and an FPGA chip, both of which still fall short of what mobile/phone arm chips achieve on density using the 7nm FF/FF+ design from TSMC as a matter of percentage (not discussing raw transistor counts, as that is a 3:1 ratio, approximately).

Getting back to Xeons, some have suggested up to 15.xMTr/mm^2 on those, which is without the iGP, and still only gives about 35% of the theoretical density on 14nm (a little higher on the "+" process variants).

So, unless you can show Intel reaching near the theoretical limit on their HPC libraries and mainstream and server options like Xeons, you are arguing that when you use an entirely different architecture on Intel's process, you can achieve higher densities, neither of which is above the 80% mark. I will agree there. But Intel is using density for marketing and misleading on being most dense in regards to their chips because of a theoretical SRAM density. In practice, the chips consumers are buying, whether the mainstream, HEDT, or server Xeon offerings, are much less dense than the theoretical limit.

Edit 2: Also, if you compare Intel's UHP libraries, under their own theoretical chart, you have a max theoretical density of 67.18MTr/mm^2, compared to TSMC's HPC 66.7MTr/mm^2. You could argue that the nearly 0.5MTr/mm^2 theoretical max density is better. But, there still are questions as to whether Intel will achieve a high enough density under that compared to those using the TSMC node.

 

[Dayman1225]

Leaked Intel Datacenter Roadmap from Huawei

Whitley Platform;

• Ice Lake SP
  • 26 Core or less
  • 8 Channel DDR4
  • PCIe4
  • Barlow Pass Optane DIMMs
  • 10nm
  • Q2 2020
• Cooper Lake SP
  • 48 Cores or Less
  • 8 Channel DDR4
  • PCIe3
  • Barlow Pass Optane DIMMs
  • 14nm
  • Q1 2020

Cedar Island Platform;

• Cooper Lake P
  • 4-8S
  • 26 Core or Less
  • 6 Channel DDR4
  • PCIe3
  • Barlow Pass DIMMs
  • 14nm
  • Q1 2020

Eagle Stream Platform

• Sapphire Rapids
  • 8 Channel DDR5
  • PCIe5
  • CXL Support
  • Crow Pass Optane DIMM
  • 10nm
  • Q1 2021
• Granite Rapids
  • 8 Channel DDR5
  • PCIe5
  • CXL Support
  • 7nm
  • Donahue Pass Optane DIMM
  • Q1 2022

 

[jpiniero]

Cedar Island Platform;

• Cooper Lake P
  • 4-8S
  • 26 Core or Less
  • 6 Channel DDR4
  • PCIe3
  • Barlow Pass DIMMs
  • 14nm
  • Q1 2020

Ah, so Charlie was right about there being two Cooper Lake platforms. Seems that Cedar Island is coming first too.

The rumor was that Icelake-SP was supposed to max out at 38 cores, but for obvious yield reasons gave up on the XCC. It's going to be a real tough sell when Rome's low end is going to be 32 cores, and I'm sure Intel knows that.

 

[DrMrLordX]

26 core IceLake? Are they going to make an AP die out of that with . . . 52 cores? 48 cores?

 

[TheGiant]

not that bad that they can do 26C with their 10nm
sounds promising
I still think they have some big bomb incoming in late 2019/early 2020