Discussion Intel current and future Lakes & Rapids thread

[Dayman1225]

Cascade Lake Refresh is likely Cooper Lake. That's one issue with that roadmap, even if legit, it's likely out of date. One theory is that they took Cascade Lake Refresh and (because of Rome) updated it to be dual die using EMIB.

This is the only time I have ever heard of a "Cascade Lake Refresh", even Intel calls it Cooper Lake publicly, so why would supposed private documents from a Dell Presentation call it "Cascade Lake Refresh". Also i'd put money on Cooper not using EMIB, just saying.

I doubt you will see Icelake Server actually make it to the wild even in a scenario where yields magically improved to say mediocre instead of terrible.

Who knows.

Once Rome ships, any big die Xeon less than 32 cores is going to be unsellable.

Lets be real here, you and I both know Intel will still ship tonnes of chips, Rome or not, because they're Intel.

I at this point think the Icelake Server that's been floating around is still monolithic.

I agree.

 

[Dayman1225]

Desktop Roadmap

View attachment 5600

Skylake SP is listed as 4 Channel, its 6 - Cascade Lake Refresh has LWS PCH instead of C620 PCH even though they are the same thing. Why list them differently? it is slide number "152 of 14". Dell's logo is being cut off at the bottom, TDP for X-Series is wrong, they go upto 165w. Also guys, its Q2 2019 and the 8c Xeon E Mehlow refresh didn't happen, Cascade launched in April of Q2, this "Roadmap" says Q1... Something does not seem right...

 

[jpiniero]

Lets be real here, you and I both know Intel will still ship tonnes of chips, Rome or not, because they're Intel.

No doubt, but it'll be Cooper.

 

[JDG1980]

So, Intel is pretty bullish about 10nm (Swan also cites 10nm ramp as a significant capital drain). I can’t see how Intel can make these claims by C-level executives (who have fiduciary responsibility) without risking the prospect of serious investor:backlash if they prove false.

Pay close attention to exactly what is being said in Murthy's statement - and what isn't. There is lots of vague puffery, but no concrete promises about deliverable dates.

"I think 10 nanometers is looking better now than at the last earnings call" - That's setting a pretty low bar, isn't it?

 

[coercitiv]

Skylake SP is listed as 4 Channel, its 6 - Cascade Lake Refresh has LWS PCH instead of C620 PCH even though they are the same thing. Why list them differently? it is slide number "152 of 14". Dell's logo is being cut off at the bottom, TDP for X-Series is wrong, they go upto 165w. Also guys, its Q2 2019 and the 8c Xeon E Mehlow refresh didn't happen, Cascade launched in April of Q2, this "Roadmap" says Q1... Something does not seem right...

Yeah, I saw your tweet. I definitely wouldn't mind if these leaks were at least partly fake, but then again Intel's official presentation doesn't really contradict them - this year it seems like we're heading for another dry season on the 10nm front, and their fast spinning factory isn't likely to help much in 2020 either, at best we'll see good 10nm volumes in Xeons for H2 2020. Desktop client offerings starting with 2021 doesn't seem that far fetched.

The day I'll start being optimistic about 10nm Intel products will be the day a high ranking Intel rep starts talking about significantly improved yields. Until then all my Intel related purchase plans will only include a new ultra-portable, no matter how good or bad ICL-U is (for my needs even Whiskey Lake checks all the marks, so I'm safe). On the desktop side winter is definitely coming.

 

[birdie]

Yeah, I saw your tweet. I definitely wouldn't mind if these leaks were at least partly fake, but then again Intel's official presentation doesn't really contradict them - this year it seems like we're heading for another dry season on the 10nm front, and their fast spinning factory isn't likely to help much in 2020 either, at best we'll see good 10nm volumes in Xeons for H2 2020. Desktop client offerings starting with 2021 doesn't seem that far fetched.

The day I'll start being optimistic about 10nm Intel products will be the day a high ranking Intel rep starts talking about significantly improved yields. Until then all my Intel related purchase plans will only include a new ultra-portable, no matter how good or bad ICL-U is (for my needs even Whiskey Lake checks all the marks, so I'm safe). On the desktop side winter is definitely coming.

Whisky Lake CPUs might be good but the UHD 620 iGPU is absolute trash. It's as fast as the entry level NVIDIA GeForce 910M GPU from ... 2015. Has Intel completely lost their mojo?

 

[Yotsugi]

Has Intel completely lost their mojo

They just never bothered making fatter iGPUs outside of Crystal well SKUs, which are used by what, Apple and Intel itself?

 

[Ajay]

I doubt you will see Icelake Server actually make it to the wild even in a scenario where yields magically improved to say mediocre instead of terrible. Once Rome ships, any big die Xeon less than 32 cores is going to be unsellable. I at this point think the Icelake Server that's been floating around is still monolithic.

Well, thats the problem, even if Intel hits a 70% yield on 4c Icelake, a 32 core ICL server cpu will still have terrible yields. On top of that, they will need some sort tech to get 64 cores per socket, which will lead to higher packaging losses. SMH.

 

[Ajay]

Pay close attention to exactly what is being said in Murthy's statement - and what isn't. There is lots of vague puffery, but no concrete promises about deliverable dates.

"I think 10 nanometers is looking better now than at the last earnings call" - That's setting a pretty low bar, isn't it?

Fair enough, the only thing Intel committed to was the ICL client being on shelves (systems) in Q4.

 

[jpiniero]

Well, thats the problem, even if Intel hits a 70% yield on 4c Icelake, a 32 core ICL server cpu will still have terrible yields. On top of that, they will need some sort tech to get 64 cores per socket, which will lead to higher packaging losses. SMH.

I imagine Cooper is more or less Cascade Lake-AP in socketed form, except the dies are connected via EMIB and 8 channel memory.

 

[birdie]

10nm(?) Comet Lake-G and U-series SKUs have been leaked.

 

[DrMrLordX]

Comet Lake shouldn't be 10nm in any form.

 

[jpiniero]

Comet Lake shouldn't be 10nm in any form.

The G would be Icelake I guess.

I'm skeptical about the model names, seems too busy, plus the 6 core i7 having a 300 mhz less turbo than the quad i7?

 

[Dayman1225]

That looks very fake...

 

[Kaloi48]

The G would be Icelake I guess.

I'm skeptical about the model names, seems too busy, plus the 6 core i7 having a 300 mhz less turbo than the quad i7?

You are right. The G models are Icelake.
The original source come from PTT message board and the information was mistranslated.

 

[jpiniero]

I should say that the very low base for the Icelake models isn't an issue for me, between the need to bin loosely and AVX-512 and also possibly the IGP.

Still, I don't know.

 

[Yotsugi]

I should say that the very low base for the Icelake models isn't an issue for me

Base clocks are whatever outside of like, server parts.

between the need to bin loosely and AVX-512 and also possibly the IGP.

Single 512b FMA isn't exactly very powerhungry.

 

[Kaloi48]

I guess the G7 models would be the Icelake with 64 EUs graphics vs. the G4 with 48 EUs and the G1 with 32 EUs.

This may be the new model naming conventions of Intel client CPU going forward.

 

[TheGiant]

low clocks on icelake? why?

 

[Yotsugi]

low clocks on icelake?

Because.

why?

Because 10nm.

 

[NostaSeronx]

low clocks on icelake? why?

Intel made certain decisions on the 10-nm node that didn't work as intended.

-> The Sunnycove architecture itself re-used Skylake-SP/Cannonlake's computational execution cluster.
// AVX512 units and 2x Store with reduced wire speed and increased heat in wires.

-> Sunnycove on 10nm makes use of COAG, Fin depopulation, and track height reduction to get extra density.
// Reduces performance and can impact yields via increased variation. If past that to get to the same speeds, more power is needed.

Luckily however 10-nm and 7-nm had different design teams, much like NetBurst and Core.

 

[TheGiant]

Intel made certain decisions on the 10-nm node that didn't work as intended.

-> The Sunnycove architecture itself re-used Skylake-SP/Cannonlake's computational execution cluster.
// AVX512 units and 2x Store with reduced wire speed and increased heat in wires.

-> Sunnycove on 10nm makes use of COAG, Fin depopulation, and track height reduction to get extra density.
// Reduces performance and can impact yields via increased variation. If past that to get to the same speeds, more power is needed.

Luckily however 10-nm and 7-nm had different design teams, much like NetBurst and Core.

so we should expect worse max frequency from intels 10nm while increasing IPC?
so the only benefit from 10nm should be less power, but 9900K performance ?

 

[Markfw]

so we should expect worse max frequency from intels 10nm while increasing IPC?
so the only benefit from 10nm should be less power, but 9900K performance ?

By the time we actually see the chips, who knows, too far off.

 

[beginner99]

so we should expect worse max frequency from intels 10nm while increasing IPC?
so the only benefit from 10nm should be less power, but 9900K performance ?

Yes. In fact at this point I think they csan't even match a 9900k in pure performance. 10nm was designed to be dense and power saving and not high clocking. Same as 14nm initially. 14nm-pluses are essentially less dense versions of intial 14nm to allow for higher clocks. I assume we will see the same thing with 10nm if it ever makes it to the desktop at all.
Intel would not spend billions on 14nm capacity if 10nm was up to speed. 10nm probably only good for laptop CPUs due to small size of the chips (yields) and being about low power not performance. Server chips are too large and desktop chips on 14nm simply clock too high to make anything on 10nm that can compete on pure performance. intels half-a decade 14nm optimizing is now biting them in the ass as they will struggle to get out something faster.

 

[coercitiv]

I should say that the very low base for the Icelake models isn't an issue for me, between the need to bin loosely and AVX-512 and also possibly the IGP.

I don't buy it: the IGP will have a lot more resources relative to memory bandwidth, hence they would likely be incentivized to drop IGP clocks for efficiency improvements. On top of that 10nm is supposed to deliver excellent power saving (up to half the power?) and Gen11 cores are reportedly smaller than Gen9.5 (indicating a 1:1 power ratio per core isn't likely), so overall we should expect the IGP power budget to remain mostly stationary relative to previous gen.

On top of everything else, traditionally CPU base clocks for U chips are based on CPU only workloads. When both CPU and GPU are pushed to their limits there's another balancer in place that is usually configured to prioritize GPU clocks over CPU clocks, and CPU frequency can go well bellow base values. (a CPU with 2.2GHz base can go to 1.1Ghz during mixed intensive workloads)

The base clocks in that table look like Y class to me, while the boost clocks are U class, although I was expecting less than 20% drop in fmax. This contradiction alone make me question the veracity of the leak.