I think you might be barking up the wrong tree. All current U/Y platforms with Thunderbolt 3 have the controller connected via the PCH, because there are no PEG lanes, so there would be no difference as far as PCIe bandwidth is concerned if Thunderbolt was integrated into the PCH. Even on the two-chip platforms, I believe Apple is the only vendor that sometimes connects Thunderbolt controllers directly to the CPU.
The additional bandwidth that an integrated Thunderbolt controller would require is in the form of 8 DisplayPort lanes. And once you think about it, it makes far more sense to integrate Thunderbolt into the CPU die and not the PCH. You could make the back-end as wide as you needed to and still not have to worry about PCIe bandwidth contention issues, and it could be presented as a Thunderbolt signaling mode on the DDI interfaces, thereby not requiring additional I/O pins. The power savings from keeping all of the PCIe and DP connections on die would be considerable, and routing for the high-speed signaling traces would be greatly simplified. In fact, if you look at the language Intel has used, they have repeatedly stated that Thunderbolt would be integrated into future CPUs, not platforms or PCHs.
Regardless of where Intel decides to put it, an integrated Thunderbolt solution will still require a companion chip. Because you can't always locate the PCH or CPU within two inches of your ports, it's going to need a high-speed mux and multi-protocol linear redriver that can support Thunderbolt 3, USB 3.2, and DisplayPort 1.4a signaling. We also have yet to see any sort of USB PD or Type-C Port Controller IP from Intel, and so I imagine that either those functions would be combined with the mux / redriver, or require additional discrete solutions. The PCH could really use a couple Type-C Port Controllers, so maybe those will go there. If Thunderbolt is indeed integrated into the CPU, I wonder if they will also include a USB 3.2 xHCI, which would go even further towards simplifying signal routing and reducing the ball count.
Do we have any idea what Icelake will be packing in terms of support for PCIe 4.0, DisplayPort 1.4a, or USB 3.2 Gen 2 x 2? I'm assuming we'll at least get LPDDR4(X) support. It would also be nice if the Gen11 GPU supported 4 display streams. If Thunderbolt is integrated at the CPU level, an additional DDI interface on the S/H platforms would also allow vendors to provide up to 4 Thunderbolt ports without requiring a discrete controller.
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