Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

Then there is Cannonlake 2 + 0, I am assuming this is a CPU only instead of having GPU silicon disabled. How is it for ?

It's for Shareholder PR so they can say they are still ahead of the foundries. They are selling test chips essentially.

 

[IntelUser2000]

There's supposedly a Cannonlake 2+2 coming for the U. But only 2 SKUs are coming, that and the 2+0. It looks like the Y chips are cancelled and we'll see 2+2 and 2+0 U as the Cannonlake launch?

 

[Dayman1225]

So the reason Skylake-X and SP cores are so large isn't just because of 1MB L2 and AVX-512. AVX-512 in terms of added area is actually relatively small.

There's also the CHA(Caching Home Agent), Snoop Filter, power management, and logic needed for the mesh. I would say about half of the new space is taken up by them. In Broadwell EP chips, the CHA and Snoop filter functions were spread elsewhere, so the cores looked similar in size to consumer Broadwell ones. With Skylake, each cores have CHA and Snoop Filters.

They are actually critical for server chips. But they aren't necessary for HEDT. The HEDT market is way too small to justify a dedicated core development though.

Going back to this, Intel apparently showcased these at ISSCC 2018 that prove your point completely

CHA is much larger than I would have imagined and AVX512 is much smaller than I was led on to believe by others.

Rest of the slides are here

 

[IntelUser2000]

CHA is much larger than I would have imagined and AVX512 is much smaller than I was led on to believe by others.

I also got it from PCWatch.

Intel could split the line into three, by going Mobile, Desktop(including HEDT) and Server.

I wonder if they can opt to go traditional MCP, or even EMIB. Rather than basing HEDT off servers that brings added memory latency, die complexity, and cost increases they can put multiple of the top Desktop die. Say if top HEDT was two 8700K dies in one package connected by EMIB. It would be just like how AMD is doing it with Threadripper. You'd lose some frequency, but have 2x the cores, 2x memory channels, and 2x PCIe lanes.

 

[jpiniero]

I guess it is more the extra L2 although they do go hand in hand. Also probably means that the Icelake Phi has even more L2 per core given that it was too big and they are cutting it to 22ish cores per die.

Icelake Server is probably too early but the "Sea of Cores" patent is I imagine where Intel is headed.

 

[Arachnotronic]

They are actually critical for server chips. But they aren't necessary for HEDT. The HEDT market is way too small to justify a dedicated core development though.

The HEDT market is too small to justify dedicated core development, but the overall desktop computer market is not. Intel likes to get a lot of leverage out of each die, but the truth is they can afford to do separate cores/SoCs for each of its major market segments (desktop, notebook, and server). The problem is that they left desktop for dead a while ago (NB shipments overtook DT shipments a while ago, and the tablet scare they saw in 2012 only accelerated that), and are now only realizing that it had a pulse.

 

[Arachnotronic]

I also got it from PCWatch.

Intel could split the line into three, by going Mobile, Desktop(including HEDT) and Server.

I wonder if they can opt to go traditional MCP, or even EMIB. Rather than basing HEDT off servers that brings added memory latency, die complexity, and cost increases they can put multiple of the top Desktop die. Say if top HEDT was two 8700K dies in one package connected by EMIB. It would be just like how AMD is doing it with Threadripper. You'd lose some frequency, but have 2x the cores, 2x memory channels, and 2x PCIe lanes.

Two 8700K dies connected would be a disaster, especially considering the redundancy such a chip would have (two uncores that can't easily be ganged together) and probably poor inter-core latency to boot (similar to what you see with Threadripper).

No, what Intel needs to do is to split the die into different subsystems and to serve the different markets, they would build SoCs with the appropriate building blocks. For a DT part they would exclude a GPU/media tile, LTE modem tie, etc. but they would bring in a CPU tile with 8+ cores for the top SKUs, 6+ for i5, and so on. They can't get out of doing the work of different sized tiles for different SKUs, but partitioning everything into separate tiles and including the appropriate tiles in the appropriate portions for each SKU would be viable.

As far as HEDT goes, same concept, but they would probably just pull in whatever tile they use for the server parts but give it a less bloated uncore.

 

[2blzd]

kinda bizarre and a little bit confusing that they're now refering to the Xeon Quads as "-E" Kaby Lake-E and Coffe Lake-E.

That used to be for HEDT chips. I can now see where the confusing leaks and confusion came from a year or so ago with kaby lake-e being a thing

 

[IntelUser2000]

The HEDT market is too small to justify dedicated core development, but the overall desktop computer market is not.

The desktop market has lots in common with the mobile market. It's not entirely clear what they can do differently on a Desktop specific core. Not too many, high frequency, latency optimized cores? Laptop and Desktops both want that. Power efficiency focused design? Both can use that. Mass integration of cheap iGPUs? Both markets use that.

No, what Intel needs to do is to split the die into different subsystems and to serve the different markets, they would build SoCs with the appropriate building blocks. For a DT part they would exclude a GPU/media tile, LTE modem tie, etc.

It wouldn't work because,

The low power, lost cost, and integrated Notebook and Desktop parts benefit tremendously from having a monolithic design over EMIB/MCM. The die sizes are small so there's no cost advantages. It may be that extra packaging costs outweigh having smaller dies. You also lose fine grained power management and use more power because interconnects have to be external.

In Clarkdale, the reason the memory controller was on the GPU portion of the die was because the GPU needed the memory controller closer. I don't seem them going back to that. On parts like Kabylake-G it works because it has both a DDR4 controller for the CPU and HBM2 controller for the GPU. There's zero advantages and all the disadvantage on a GT2 class part that doesn't aim for the best graphics performance and doesn't have a separate VRAM.

 

[Justinbaileyman]

When are the new Intel CPU's and Z390 motherboards due to release again? We are expecting 8c/16t this time around correct??

 

[LTC8K6]

When are the new Intel CPU's and Z390 motherboards due to release again? We are expecting 8c/16t this time around correct??

Sometime this year, and maybe.

 

[Justinbaileyman]

Sometime this year, and maybe.

LOL , OK first half or second half?? or is it a toss up right now??

 

[LTC8K6]

LOL , OK first half or second half?? or is it a toss up right now??

Supposed to be 1H18 for Z390, and 8 cores seems very vaporish at this time...

 

[Justinbaileyman]

Awww gotcha, thank you for your reply sir!!

 

[jpiniero]

The low power, lost cost, and integrated Notebook and Desktop parts benefit tremendously from having a monolithic design over EMIB/MCM. The die sizes are small so there's no cost advantages.

70-110 mm2 isn't small. Not anymore. Unless Intel intends to go smaller than that, client dies using EMIB makes sense. It may only be PCH <-> CPU <-> GPU but that would be good enough.

 

[IntelUser2000]

Supposed to be 1H18 for Z390, and 8 cores seems very vaporish at this time...

1H18 for the mainstream 300 series chipsets. Likely Q3 for Z390.

https://wccftech.com/intel-coffee-lake-300-series-z370-z390-chipset-leak/

They aren't going to release Z390 in Q1 when Z370 has been launched less than 6 months ago.

70-110 mm2 isn't small. Not anymore.

Sure it is. Packaging costs dominate at that die size.

 

[LTC8K6]

1H18 for the mainstream 300 series chipsets. Likely Q3 for Z390.

https://wccftech.com/intel-coffee-lake-300-series-z370-z390-chipset-leak/

They aren't going to release Z390 in Q1 when Z370 has been launched less than 6 months ago.



Sure it is. Packaging costs dominate at that die size.

"supposed to be" means it will not be, of course.
Q1 is not the same as 1H.
wccftech is generally not a reliable source.
Intel will release when Intel releases.

 

[IntelUser2000]

"supposed to be" means it will not be, of course.
Q1 is not the same as 1H.
wccftech is generally not a reliable source.
Intel will release when Intel releases.

Wccftech isn't always unreliable. Second, even if they are unreliable, the information may not be.

All indications show its a legitimate Intel slide. Of course there are people who disregard all leaks as fake until its released.

Rule of thumb is minimum of 12 months between releases, because that's the optimal time for sales and revenue. In certain exceptional circumstances, manufacturers hasten release(Core 2, Coffeelake), but not always. In some cases, like with Coffeelake, Intel hastily released Z370 because the real 300 chipset release would be 4-5 months away.

Z370 - August 2017 makes Z390 in Q3 of that year. Roughly 12 months.

 

[LTC8K6]

https://www.tweaktown.com/news/59851/intels-next-gen-z390-ready-coffee-lake-1h-2018/index.html

Intel's next-gen Z390: ready for Coffee Lake-S in 1H 2018

Given the footnote and Intel's situation, I think we will see Z390 right at the end of 1H18.

 

[Bouowmx]

Some time within the previous week, processors got ahead of the motherboards: https://videocardz.com/75095/new-coffee-lake-cpus-already-in-stock-and-shipping

 

[jpiniero]

https://www.tweaktown.com/news/59851/intels-next-gen-z390-ready-coffee-lake-1h-2018/index.html

Intel's next-gen Z390: ready for Coffee Lake-S in 1H 2018

Given the footnote and Intel's situation, I think we will see Z390 right at the end of 1H18.

That's from November though and probably out of date. Intel appears to be flip-flopping on Coffee Lake Refresh vs Icelake for 9th gen desktop but we'll have to see. If they do indeed do Coffee Lake Refresh, August would make sense and also release z390 then.

 

[IntelUser2000]

Some time within the previous week, processors got ahead of the motherboards: https://videocardz.com/75095/new-coffee-lake-cpus-already-in-stock-and-shipping

That doesn't indicate launch. I think they'll all come at the same time. It's same deal with the new Optane devices(800P and M10). Many vendors already have it listed, but its not launched. It's been like that for weeks.

On eBay, you can even order the M10 drive.

The next possible date starts on 26th of February at Morgan Stanley TMT Conference 2018. It may be just Optane SSDs because its the NVMe guy from Intel presenting, but a platform launch alongside it could be perfect. 26th may be the presentation, with 300-series chipset and mainstream CFL release happening over the week(because it lasts until March 1st).

 

[mikk]

https://www.notebookcheck.net/Intel-reveals-protorype-of-their-discrete-GPU.284754.0.html
https://hexus.net/tech/news/graphics/115436-intel-showcases-14nm-discrete-gpu-prototype/
https://wccftech.com/intels-prototype-dedicated-gpu-details-announced-at-isscc/
https://pc.watch.impress.co.jp/docs/column/kaigai/1107078.html


Intel explained their first discrete GPU 14nm protoype at ISSCC 2018.

 

[PeterScott]

70-110 mm2 isn't small. Not anymore. Unless Intel intends to go smaller than that, client dies using EMIB makes sense. It may only be PCH <-> CPU <-> GPU but that would be good enough.

It's very small. AMD's APU is twice that size.

Until you go large, MCM is mainly a pointless distraction.

The most obvious potential cut line is removing the GPU to a separate chip, and yet everything in recent years has been all about integrating this.

 

[jpiniero]

It's very small. AMD's APU is twice that size.

Yeah but AMD's APUs are on a node that works. That's sort of the problem, especially when yields are only going to get worse as (if?) the shrinks continue. One of the big benefits to an EMIB design is that you could have some tiles on older nodes.