Intel Cannonlake, Ice Lake, Tiger Lake & Sapphire Rapid Thread

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Markfw

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not that bad that they can do 26C with their 10nm
sounds promising
I still think they have some big bomb incoming in late 2019/early 2020
It said 14 nm. They already have a 28 core 14 nm, so I don't see the big deal.
 
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jpiniero

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With 26c Max I’m not quite sure how this works but...
Hmm, well if Cooper on Whitley is going to be 350+ W TDP, I suppose they could offer similarly high TDP models for Icelake even though it has half the cores, with a juiced up AVX-512 clock as the main beneficiary.
 
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Bouowmx

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Whitley is only a 1-year platform. hmm

Cooper Lake-P with more UPI sounds like it should be the normal SP. Cooper Lake-SP with 48 cores sounds like it should be AP.

26 cores sounds like the current 5x6 mesh minus 2, and minus 2 more.
 

TheGiant

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Jun 12, 2017
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well I am not convinced that everyone wants moar coarz....
there are lots of software with license based on core count

if Intel can deliver per core/thread count much higher performance it has a big selling potential
ofc pure cloud VMs and epyc 64C are in love, there intel doesn't reach, only if they offer something with EMIB/foveros/whatever....or the glue
 
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IntelUser2000

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I thought we were talking about fmax potential and frequency ceiling of 10n / 7nm, not whether the architecture needs improvement or not.
Ah, I see what you were referring to now. There's a very important difference between SNB and CFL there too. The former had great OC headroom. The latter achieves "high clocks" by simply eating up headroom. Unchanging uarch/process would have meant insane amount of time to characterize the silicon to maximize out of box frequency.

When Intel said they were abandoning Netburst because clock and voltage scaling was dead, its true today as it was then.

ajc9988 said:
But Intel is using density for marketing and misleading on being most dense in regards to their chips because of a theoretical SRAM density.
Yes they can. And I don't think its SRAM they are referring to, because 14nm SRAM didn't get the claimed density benefits over 22nm SRAM cells, and it was the historical 45-50% reduction. But I know one chip that did.

Atom. The 14nm Airmont core got an amazing 64% reduction in size compared to the 22nm Silvermont one. That's 2.78x the density, just like it was claimed: chrome-extension://oemmndcbldboiebfnladdacbdfmadadm/https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-intels-technology-leadership.pdf

The Goldmont core, even with substantial advancement over Airmont, is still small enough that you can fit 6-7 of them in the size of one Skylake-class core. Or putting it another way, you could fit nearly 4 Goldmont cores, its L2 caches, and the System Agent equivalent in 1 Skylake core without the L3 cache.

The density focus in a way did pay off in some aspects. It's just that its less than expected because phones went nowhere.

DrMrLordX said:
26 core IceLake? Are they going to make an AP die out of that with . . . 52 cores? 48 cores?
They don't have to. This is what I meant by preventing cannibalization. By keeping Icelake at 26 cores, you still give a reason for vendors to buy Cooper Lake. Rather than allowing Broadwell-C to be at high clocks, have the GT3e GPU and eDRAM, they kept the TDP low and clocks low so Skylake desktop would have its place.
 
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ajc9988

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Ah, I see what you were referring to now. There's a very important difference between SNB and CFL there too. The former had great OC headroom. The latter achieves "high clocks" by simply eating up headroom. Unchanging uarch/process would have meant insane amount of time to characterize the silicon to maximize out of box frequency.

When Intel said they were abandoning Netburst because clock and voltage scaling was dead, its true today as it was then.



Yes they can. And I don't think its SRAM they are referring to, because 14nm SRAM didn't get the claimed density benefits over 22nm SRAM cells, and it was the historical 45-50% reduction. But I know one chip that did.

Atom. The 14nm Airmont core got an amazing 64% reduction in size compared to the 22nm Silvermont one. That's 2.78x the density, just like it was claimed: chrome-extension://oemmndcbldboiebfnladdacbdfmadadm/https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-intels-technology-leadership.pdf

The Goldmont core, even with substantial advancement over Airmont, is still small enough that you can fit 6-7 of them in the size of one Skylake-class core. Or putting it another way, you could fit nearly 4 Goldmont cores, its L2 caches, and the System Agent equivalent in 1 Skylake core without the L3 cache.

The density focus in a way did pay off in some aspects. It's just that its less than expected because phones went nowhere.



They don't have to. This is what I meant by preventing cannibalization. By keeping Icelake at 26 cores, you still give a reason for vendors to buy Cooper Lake. Rather than allowing Broadwell-C to be at high clocks, have the GT3e GPU and eDRAM, they kept the TDP low and clocks low so Skylake desktop would have its place.
So, first, SRAM is what is usually used to qualify density for fans, hence SRAM being discussed. Second, comparing the density of two products does NOT look at the density achieved relative to the stated density on a process node. By that, I mean relative density between generations does not speak to node density or being able to achieve the published densities on a node, thereby making the comparison superfluous to the discussion of actually achieving claimed densities. So the argument makes no sense. Third, comparing a mobile type processor to a desktop on size doesn't speak to density nor is it a proper comparison. It's like comparing an Apple A12 or a Kirin to a Zen 2. Due to differences in FF process vs HPC process, different libraries, etc., you are comparing a way more dense product to one that cannot and will never achieve the same density on that node.

As to ice lake rumors, they are nice, but I have my doubts. What we know is 1) Intel is only producing dual and quad core low power chips on this process this year, 2) ice lake transistor performance, likely 10nm+, performs worse than 14nm, 3) capacity is limited, which is why 14nm will be sold along side the 10nm chips, why mainstream will not have 10nm offerings, and why mobile is the other offering besides Xeons, and 4) Intel has pushed off 10nm for years and has had trouble increasing the core count. I find it dubious, without going chiplets on active interposer, of them achieving a 26-core monolithic die considering yields of the 28-core monolithic die on the mature 14nm node is only around 35%.
 
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JoeRambo

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Jun 13, 2013
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well I am not convinced that everyone wants moar coarz....
there are lots of software with license based on core count

if Intel can deliver per core/thread count much higher performance it has a big selling potential
ofc pure cloud VMs and epyc 64C are in love, there intel doesn't reach, only if they offer something with EMIB/foveros/whatever....or the glue
There is definately truth to this statement, but consider the following: once AMD has near parity in IPC, no longer has gotchas with NUMA, has wattage advantages etc, there comes a moment where extra core count is a bonus in itself. Sure that 26C ICL is nice, but even in our non-cloud business, having lets say 48C EPYC at decent price would be very tempting even if said processor had only 90% of performance with our current total load of 20C worth of performance. Half of Epyc cores would be left for future growth and Intel would not have room for scaling any more.

In server room, capacity for load future expansion and handling load spikes is a thought after property, that goes through usual price/value considerations.
 

DrMrLordX

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They don't have to. This is what I meant by preventing cannibalization. By keeping Icelake at 26 cores, you still give a reason for vendors to buy Cooper Lake. Rather than allowing Broadwell-C to be at high clocks, have the GT3e GPU and eDRAM, they kept the TDP low and clocks low so Skylake desktop would have its place.
Is 26c IceLake going to be as scarce as Broadwell-C? That chip was mostly non-existent. It shipped in volumes far below that of Skylake. Broadwell-C wasn't going to cannibalize anything.
 

JoeRambo

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Is 26c IceLake going to be as scarce as Broadwell-C? That chip was mostly non-existent. It shipped in volumes far below that of Skylake. Broadwell-C wasn't going to cannibalize anything.
I would not focus on full 26C die being enabled and sold. Currently for example there are plenty of XCC derived Xeon products that overlap with MCC core range. It's not the full core count parts that moves most product, but those XX30-48 HP/DELL servers. Even if we step in cloud providers, they get "special" parts, but usually those are not fully functional ones ( like CLoudfrare "off-roadmap' magic 24C parts ).
 

DrMrLordX

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I would not focus on full 26C die being enabled and sold.
Okay, I guess I should rephrase my question to include any of the mid-to-high density IceLake server SKUs. I'm still flabbergasted that IceLake server can exist at all when Intel has no IceLake desktop parts in 2020 and only 4c mobile parts in quantities that are allegedly going to be pretty limited.
 

ajc9988

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Okay, I guess I should rephrase my question to include any of the mid-to-high density IceLake server SKUs. I'm still flabbergasted that IceLake server can exist at all when Intel has no IceLake desktop parts in 2020 and only 4c mobile parts in quantities that are allegedly going to be pretty limited.
Part of that is capacity, the other part competition. For the capacity part, due to yields and due to the number of fabs capable of producing 10nm designs, you can only produce certain lines, not all lines for all markets. Further, Intel has planned for years to switch to server being served first before mainstream. And due to limited capacity, you would target the highest margin parts. Hence, Xeons. As to competition, Intel has been the main chip provider for x86 based tablets, netbooks, and notebooks. Due to their 14nm capacity issues, it hit laptop manufacturers hard, causing them to expand AMD offerings. So Intel feels pressured to address that threat first.

I still question manufacturing capabilities for HCC and XCC segments, but that should answer the reason why those segments.
 
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jpiniero

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And due to limited capacity, you would target the highest margin parts. Hence, Xeons.
Are the margins really better if you only get like 5 sellable chips per wafer, and that includes partially disabled? That's why I've been saying it's more for Shareholder PR than anything else.
 

ajc9988

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Are the margins really better if you only get like 5 sellable chips per wafer, and that includes partially disabled? That's why I've been saying it's more for Shareholder PR than anything else.
Margins are better, as a wafer costs $11000 and their current 28-core chips fetch $10,800. If you limit the line so that you make it back on a single good chip, and a couple partially disabled, you would be OK. Not great on margin, but better than selling each desktop chip at $500-1000 while competing with Zen 2.

Edit: or zen 3.
 

IntelUser2000

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Second, comparing the density of two products does NOT look at the density achieved relative to the stated density on a process node. By that, I mean relative density between generations does not speak to node density or being able to achieve the published densities on a node, thereby making the comparison superfluous to the discussion of actually achieving claimed densities.
Yes, but I'm saying that they can, and probably Atoms reach the stated density. Because its those chips that offer amazing density gains far more than the historical gains.

It is mobile, and the power points make it not directly comparable, but its a proof that their claims that 14nm was that dense isn't false, its just that its not applicable for everything.

DrMrLordX said:
I'm still flabbergasted that IceLake server can exist at all when Intel has no IceLake desktop parts in 2020 and only 4c mobile parts in quantities that are allegedly going to be pretty limited.
I don't think its that surprising. They said the improvement in the past few months have been greater than expected a few months ago before that. They were also talking about being able to ship more than expected.

Clearly, they still have issues, but maybe not as catastrophic as some make it out to be. It went from being a disaster to just being bad?

Server parts are large dies, but they don't clock very high. Mobile needs to be efficient, but they have small dies. Both server and mobile are higher margin. Desktops have less priority because the requirements are the most stringent - Lower margin, and the highest clocks. You are trying to sell to a price sensitive market that demands the highest clocks.

In client, its said to be almost crazy to use HBM2 and even 1 stack version in KBL-G is expensive. Yet the GP100 adopted it fully, and with a high clocked version too. Being its a $10K part, Nvidia could more than justify the increased expenses.

I would not focus on full 26C die being enabled and sold.
Nonsense. You don't put "26 core die but you can use only 22 cores" on a roadmap. If that's a relevant roadmap, then we'll see a 26 core SKU. They don't have to ship a lot of them.
 
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JoeRambo

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Nonsense. You don't put "26 core die but you can use only 22 cores" on a roadmap. If that's a relevant roadmap, then we'll see a 26 core SKU. They don't have to ship a lot of them.
I meant exactly the same, being non native English speaker is hard to find exact words. I doubt anyone but Intel has statistics, but in HP/DELL 2U server market most of XCC dies are sold as those lower tier CPUs, same will happen with ICL
 

Ajay

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I guess if they are getting one or two working dice per wafer then that would explain it.
2 working dice per wafer would still be catastrophic. 26 cores per die on 10 nm is going to be, what, ~150 DPW - ballpark? Even a miserable yield of 15% would only garner ~20 dice per wafer - just terrible.
 

DrMrLordX

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2 working dice per wafer would still be catastrophic. 26 cores per die on 10 nm is going to be, what, ~150 DPW - ballpark? Even a miserable yield of 15% would only garner ~20 dice per wafer - just terrible.
I'm not sure how the industry measures yield rate when the node is being used on different die sizes. If you have 15% yield on 2c dice, unless all the "good" dice come from the same region of the wafer on every wafer, there's no way you get 15% actual yields when you try 26c dice on the same wafer using the same process. Someone else (sorry, I forget who) on these forums ran the math, and the wafer costs are low enough that one 26c die per wafer would at least pay for the wafer (if not R&D, packaging, shipping, etc). Two dice would actually turn a tiny profit. It would be enough to at least bamboozle investors into believing that 10nm is "just fine".
 

Ajay

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I'm not sure how the industry measures yield rate when the node is being used on different die sizes. If you have 15% yield on 2c dice, unless all the "good" dice come from the same region of the wafer on every wafer, there's no way you get 15% actual yields when you try 26c dice on the same wafer using the same process. Someone else (sorry, I forget who) on these forums ran the math, and the wafer costs are low enough that one 26c die per wafer would at least pay for the wafer (if not R&D, packaging, shipping, etc). Two dice would actually turn a tiny profit. It would be enough to at least bamboozle investors into believing that 10nm is "just fine".
I was just spitballing (we don’t know any 10nm yield data). If Intel is actually getting something like 15% yields on Y/U processors, then Icelake-SP is just another dog and pony show. 1 or 2 dice per wafer is catastrophic.
 

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