Intel Cannonlake, Ice Lake, Tiger Lake & Sapphire Rapid Thread

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repoman27

Junior Member
Dec 17, 2018
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The TB3 would be on the PCH. They would have to increase the bandwidth between the PCH and processor however, but that is doable.
I think you might be barking up the wrong tree. All current U/Y platforms with Thunderbolt 3 have the controller connected via the PCH, because there are no PEG lanes, so there would be no difference as far as PCIe bandwidth is concerned if Thunderbolt was integrated into the PCH. Even on the two-chip platforms, I believe Apple is the only vendor that sometimes connects Thunderbolt controllers directly to the CPU.

The additional bandwidth that an integrated Thunderbolt controller would require is in the form of 8 DisplayPort lanes. And once you think about it, it makes far more sense to integrate Thunderbolt into the CPU die and not the PCH. You could make the back-end as wide as you needed to and still not have to worry about PCIe bandwidth contention issues, and it could be presented as a Thunderbolt signaling mode on the DDI interfaces, thereby not requiring additional I/O pins. The power savings from keeping all of the PCIe and DP connections on die would be considerable, and routing for the high-speed signaling traces would be greatly simplified. In fact, if you look at the language Intel has used, they have repeatedly stated that Thunderbolt would be integrated into future CPUs, not platforms or PCHs.

Regardless of where Intel decides to put it, an integrated Thunderbolt solution will still require a companion chip. Because you can't always locate the PCH or CPU within two inches of your ports, it's going to need a high-speed mux and multi-protocol linear redriver that can support Thunderbolt 3, USB 3.2, and DisplayPort 1.4a signaling. We also have yet to see any sort of USB PD or Type-C Port Controller IP from Intel, and so I imagine that either those functions would be combined with the mux / redriver, or require additional discrete solutions. The PCH could really use a couple Type-C Port Controllers, so maybe those will go there. If Thunderbolt is indeed integrated into the CPU, I wonder if they will also include a USB 3.2 xHCI, which would go even further towards simplifying signal routing and reducing the ball count.

Do we have any idea what Icelake will be packing in terms of support for PCIe 4.0, DisplayPort 1.4a, or USB 3.2 Gen 2 x 2? I'm assuming we'll at least get LPDDR4(X) support. It would also be nice if the Gen11 GPU supported 4 display streams. If Thunderbolt is integrated at the CPU level, an additional DDI interface on the S/H platforms would also allow vendors to provide up to 4 Thunderbolt ports without requiring a discrete controller.
 

jpiniero

Diamond Member
Oct 1, 2010
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I am pretty sure the PCIe lanes on U/Y (currently anyway) are on the processor die and not on the package PCH.
 

jpiniero

Diamond Member
Oct 1, 2010
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Oh and my expectation is that Intel will skip PCIe 4 completely. Tigerlake probably has PCIe5 (and DDR5) but that is just speculation.
 

repoman27

Junior Member
Dec 17, 2018
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I am pretty sure the PCIe lanes on U/Y (currently anyway) are on the processor die and not on the package PCH.
Nope, no PEG lanes, just OPI, and all of the available PCIe lanes come off of the PCH.
 

jpiniero

Diamond Member
Oct 1, 2010
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Nope, no PEG lanes, just OPI, and all of the available PCIe lanes come off of the PCH.
Ah, looks like you are right; but yes the bandwidth isn't there right now.

Putting Thunderbolt on the CPU die would make it bigger, and given how yields are on 10 nm... Dumping OPI and using EMIB would make a ton of sense.
 

Bouowmx

Senior member
Nov 13, 2016
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Whiskey Lake block diagram

Latest generation abandons Imaging/IPU for PCIE lanes direct from CPU.
 

repoman27

Junior Member
Dec 17, 2018
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Ah, looks like you are right; but yes the bandwidth isn't there right now.

Putting Thunderbolt on the CPU die would make it bigger, and given how yields are on 10 nm... Dumping OPI and using EMIB would make a ton of sense.
As I mentioned before though, the bandwidth that isn't there right now is DP (DDI) not PCIe (OPI).

I'm not convinced that we'll see any real changes from CNP-LP for the Icelake Y/U PCH, but if it does get PCIe 4.0, then Intel would simply bump the OPI up to 8 GT/s. Using EMIB for an OPI x8 connection doesn't make any sense at all and would cost way more than just using a conventional package substrate for little to no benefit. Even if you ignore the additional I/O requirements, Thunderbolt would take up far more die area in a 14nm PCH than in a 10nm CPU. So I guess it would depend on whether Intel sees defect densities for a 4+2 die on 10nm+ or their current 14nm capacity crunch as being a bigger threat to revenue.

A chrisdar post from over a year ago suggested the following:

ICL-Y 4+2, 5.2W, BGA1377, LPDDR4-3733, 3x USB-C
ICL-U 4+2, 15W, BGA1526, DDR4-3200, 4x USB-C

With USB-C apparently being fully capable Thunderbolt 3 ports. If Intel integrates Thunderbolt into the CPU, each port could have the equivalent of 4 lanes of PCIe 4.0 and 8 lanes of DisplayPort HBR3 (i.e. 2x DDI) on the back end with no need for any off-die I/O.

It also appears that USB 3.2 Gen 2 x 2 may not have made the cut for ICL, and ICL-U 4+2 engineering samples are running at 20W, so Intel may have missed the initial target for TDP.
 

jpiniero

Diamond Member
Oct 1, 2010
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So I guess it would depend on whether Intel sees defect densities for a 4+2 die on 10nm+ or their current 14nm capacity crunch as being a bigger threat to revenue
The 14 nm capacity issues should be long gone by the time Icelake ships, especially with them converting most (nearly all?) the 10 nm production lines they had setup.

I do agree that sticking with the MCM with OPI getting a decent boost in bandwidth is most likely.
 
Mar 10, 2006
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The 14 nm capacity issues should be long gone by the time Icelake ships, especially with them converting most (nearly all?) the 10 nm production lines they had setup.
Do you have a source for the bolded claim?
 

jpiniero

Diamond Member
Oct 1, 2010
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Did they say most of their 10nm? Or even all? I can't find that verbiage in any of their public statements.
Intel didn't get that specific. But you would have to think they didn't have that many production lines setup and waiting to go given they were still in testing mode when they made the move to convert.
 
Mar 10, 2004
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IIRC, it was 14nm packaging capability that they needed more of, not 14nm mfg?
 

mikk

Platinum Member
May 15, 2012
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PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480
PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481
PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482
PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483
PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484
PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487
PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486
PCI_DEVICE_ID_INTEL_ICL_ID_U, "Icelake-U
PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2
PCI_DEVICE_ID_INTEL_ICL_ID_Y, "Icelake-Y
PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, "Icelake-Y-2
Lots of different versions, looks like Intel is building 2+2 SKUs as well beside 4+2. This is curious:

PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62
PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2_5
PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, "Icelake U GT3

This is the first time I hear something about a GT3 version, I wonder if they plan to add a GT3 SKU at some point.

X86_VENDOR_INTEL, CPUID_ICELAKE_A0
X86_VENDOR_INTEL, CPUID_ICELAKE_B0

CPUID_ICELAKE_A0 0x706e0
CPUID_ICELAKE_B0 0x706e1
BO stepping :)
 

jpiniero

Diamond Member
Oct 1, 2010
6,095
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Dual core U was inevitable because of the yields.

Maybe the 64 EU version is GT3 while the GT2 and GT2.5 48 EU? There's supposed to be 32 EU variants as well.
 

mikk

Platinum Member
May 15, 2012
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GT2 has 64 EUs, there are GT1.5, GT1 etc. listed as well for below 64 EU configs.
 
Apr 27, 2000
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A GT3 with no CrystalWell would be interesting. That could be a ph4t iGPU. 96 EUs?
 
Sep 9, 2017
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Does this mean we can expect Ice Lake S soon after, or not?
 

jpiniero

Diamond Member
Oct 1, 2010
6,095
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GT2 has 64 EUs, there are GT1.5, GT1 etc. listed as well for below 64 EU configs.
Thing is, actually having all 64 EUs enabled is going to be rare due to the yields you would have to think. So there's got to be more to it.
 

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