- Apr 1, 2015
If you are going to mention size *laughs like a teenage boy for a second*, you need to also discuss latency. With the 16MB L3 currently, there is 40ns of latency. For the 32MB upcoming, it is 47ns latency. So it may be bigger, but it is also slower.It is a victim cache for sure. Inclusive L3 makes no sense with those sizes. Overall rather anemic increase in cache sizes over Skylake on 14nm. 128KB more of L3 and 256KB more of L2 per core? I guess Intel in their quest to increase core counts and include AVX512 units have put caches on diet.
All while AMD core enjoy massive 4MB of L3 per core out of 16MB total, soon to be improved to 32MB total.
Does not bode well for Intel. I have expected more from 10nm in 2020.
Now, AMD can take it because of the chiplet design and ram latency with their design. But Intel has much lower memory latency (faster) than AMD with the monolithic die and the integrated memory controller right there.
Because of this, if Intel made caches too large, the cache seek times go up which would slow their time to just go to ram. It's a balancing act.
Also, intel's L2$ is way faster than their L3 or AMD's L3$. So having that be larger actually does show a speed up over a smaller L2.
Once Intel starts stacking, this might change, but instead of using MCM, they seem like they want to use an active interposer with cache and I/O on that chip shared between their big and little cores (Lakefield IIRC). This might increase seek marginally, but less than going to the I/O die for AMD. The TSV is faster. So, what the proper amount of L3 is may still be lower than AMD. This is especially true if 1GB L4 or ddr or sram or something is stuck on the chip before the longer trip and there is a proper memory prefetch for that.
But that's kind of getting into the weeds there.