Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

How about the 10nm wafers going to Xe? Aren't those significant enough, seeing they have to honor contract obligations and all?

Ponte Vicchio is using 7 nm.

 

[Zucker2k]

Contract obligations to whom?

Wasn't there news of a certain super computer contract using Xeon and Xe on 10nm?

 

[coercitiv]

Wasn't there news of a certain super computer contract using Xeon and Xe on 10nm?

in 2021

 

[lobz]

Wasn't there news of a certain super computer contract using Xeon and Xe on 10nm?

What exactly are you talking about? Can you find me those news?

 

[Adonisds]

What exactly are you talking about? Can you find me those news?

Wasn't there news of a certain super computer contract using Xeon and Xe on 10nm?

Intel’s 2021 Exascale Vision in Aurora: Two Sapphire Rapids CPUs with Six Ponte Vecchio GPUs

www.anandtech.com

 

[Adonisds]

Intel’s 2021 Exascale Vision in Aurora: Two Sapphire Rapids CPUs with Six Ponte Vecchio GPUs

www.anandtech.com

That makes me remember that Aurora was initially supposed to come in 2018 with Knights Hill on 10nm. Doesn't Intel get punished by breaking the contract with these delays?

 

[IntelUser2000]

Wouldn't that be enough? I agree that the off-die IMC/iGPU will be a sidegrade (with the benefit of some better memory speed support, and maybe some better graphics). But I do not think the power penalty of relying on EMIB to connect the dice will be so great that a 25% reduction in power usage of the IMC and iGPU would be insufficient to offset that penalty.

Hmm, I meant 25% in that quarter of the battery life gain is due to process, so 2.5% if the new platform offers 10% gain in battery life.

Also you must differentiate between power consumption and battery life. Battery life typically means in bursty usage scenarios where the CPU can idle in between. Because it only needs to be active for fraction of the time, the system idle power use becomes the dominant one. Process gains affect load the most, so the impact is diminished.

It's simply physics why off-die uses more power. If lot of the battery life deficiency relative to ARM is because Intel chips having a two-chip(on package PCH) setup, how do you think a 3-chip solution will do? Off-die means it transitions between C-states slower, meaning less scenarios where it can go to idle, and the interconnect itself would increase idle power.

As someone already mentioned in the forums, this sunken cost fallacy at it's finest. (and not something to criticize Intel about, but rather something to learn from)

I'm not sure if that can be said, because they finally got it into mass production state. If Icelake were to be another Cannonlake, I would wholeheartedly agree.

Know what they say. In theory practice and theory are the same, but in practice its not. The same reason pipe cleaner products exist. Without the learnings of 10nm being in mass production, I don't believe successors are possible. I even think its a good thing they got that single Cannonlake out so it can be characterized in practice how it does.

 

[IntelUser2000]

Most of the 10nm Ice-Lakes I've seen in the wild are from Dell XPS lineup.

You are missing quite a bit then. The Inspiron 3000 and 5000 are both available with Icelake, and due to their price will be higher volume than the XPS lineup. Whiskey Lake laptops are plenty, but Comet Lake has much lower volume.

Best Buy also shows there are HP laptops without the fancy names("HP 14") using Icelake, and Lenovo IdeaPads with it too.

If you look at DrMrLordX's thread, you even have $300 laptops coming with the Core i3 Icelake, meaning they are likely using some Icelake chips to fulfill the demand that 14nm chips can't.

 

[Gideon]

You are missing quite a bit then. The Inspiron 3000 and 5000 are both available with Icelake, and due to their price will be higher volume than the XPS lineup. Whiskey Lake laptops are plenty, but Comet Lake has much lower volume.

Best Buy also shows there are HP laptops without the fancy names("HP 14") using Icelake, and Lenovo IdeaPads with it too.

If you look at DrMrLordX's thread, you even have $300 laptops coming with the Core i3 Icelake, meaning they are likely using some Icelake chips to fulfill the demand that 14nm chips can't.

I never said these are the only laptops. just the ones that are the most available here. And yes, they are using them to alleviate demand on 14nm but the bottom line is still that Dell gets less and less chips every quarter.

 

[jpiniero]

You are missing quite a bit then. The Inspiron 3000 and 5000 are both available with Icelake, and due to their price will be higher volume than the XPS lineup. Whiskey Lake laptops are plenty, but Comet Lake has much lower volume.

Almost wonder if Intel made a big mistake going to six cores with Comet Lake U.

 

[DrMrLordX]

Wasn't there news of a certain super computer contract using Xeon and Xe on 10nm?

Sapphire Rapids is going to be 10nm. Ponte Vecchio is going to be 7nm. As stated by @jpiniero .

Off-die means it transitions between C-states slower, meaning less scenarios where it can go to idle, and the interconnect itself would increase idle power.

Depends on the idle state? If the system has entered sleep mode, you would think the interconnect could be powered down. Heck, ARM's DynamIQ already lets you power down some or all L3 cache via power gating. Pretty sure they let you power down entire core clusters and all interconnects to them as well.

 

[coercitiv]

Know what they say. In theory practice and theory are the same, but in practice its not. The same reason pipe cleaner products exist. Without the learnings of 10nm being in mass production, I don't believe successors are possible. I even think its a good thing they got that single Cannonlake out so it can be characterized in practice how it does.

Again, this is not about whether 10nm is functional or not, it's about whether or not Intel's 10nm capacity & yields are able to offset the huge 14nm demand they're seeing, so huge they are publicly apologizing, so huge that Dell is forced to announce they're missing financial targets. As I said before, I never viewed the new node capacity as a necessity to fill demand for the old node (in case of semi-failure), I always considered the new node to be either the main driver of consumer demand or simply a failure that inherently lowers demand anyway. (in favor of the competition, if any)

This is a risk I never took into account, but top tier managers likely did and decided to go through with 10nm anyway. Maybe they did the math and considered today's loss will be offset by tomorrow's wins, maybe they just went ahead because "sunken cost".

 

[IntelUser2000]

Depends on the idle state? If the system has entered sleep mode, you would think the interconnect could be powered down. Heck, ARM's DynamIQ already lets you power down some or all L3 cache via power gating. Pretty sure they let you power down entire core clusters and all interconnects to them as well.

L3 caches are on-die. So are everything in ARM mobile chips.

It sounds like you can power down the off-die chips just as readily, but it never worked in practice. Simple laws of physics dictate that. It transitions between states slower, which means less applications that can be considered "bursty".

If you read forums, some laptops have trouble working with the C8 state, nevermind the deepest C10. That should give you an idea of making it work in real, shipping systems.

This is bad. They are behind with a 4GB/s bandwidth off-die PCH. Now try to do the same with 70GB/s graphics and memory controller off-die too.

This is a risk I never took into account, but top tier managers likely did and decided to go through with 10nm anyway. Maybe they did the math and considered today's loss will be offset by tomorrow's wins, maybe they just went ahead because "sunken cost".

I'm a little surprised by this response. It sounds like you are saying canning 10nm would have been a better idea.

No, this is less of the evils. Because alternative would mean waiting for 7nm, which never will happen because that's a 5x density jump from 14nm and that nearly guarantees complete end. And secondly, sticking with Cometlake and Rocketlake instead of Icelake, and Tigerlake which is far superior.

 

[mikk]

In the newest drivers there is a new appearance of Alder Lake:

Alder Lake-S
Alder Lake-UH

 

[uzzi38]

Ah yes, I too look forwards to the arrival of the broadwell-tier volume meme also known as ADL-S.

But hey, they gotta show somehow that everything is fine after Zen 3's launched and Zen 4 is so soon over the horizon.

 

[A///]

Ah yes, I too look forwards to the arrival of the broadwell-tier volume meme also known as ADL-S.

But hey, they gotta show somehow that everything is fine after Zen 3's launched and Zen 4 is so soon over the horizon.

Zen3 is going to be interesting. If the current rumors flying about are true, then it's going to be harder to procure a high end but not high end mainstream chip like a 4800X. I was going to buy a 3800X on sale today but I chose not to. If I waited 3 years to see where AMD will be, I can wait another six to seven months.

 

[jpiniero]

Ah yes, I too look forwards to the arrival of the broadwell-tier volume meme also known as ADL-S.

But hey, they gotta show somehow that everything is fine after Zen 3's launched and Zen 4 is so soon over the horizon.

I wouldn't read much into it other than they actually thought they would release Alder Lake-S at one point. There's not much downside to leaving support in there in case they (yes) decide to revive it for whatever reason.

 

[mikk]

I wouldn't read much into it other than they actually thought they would release Alder Lake-S at one point.

The addition of ADL is relatively new in public drivers, and it's not a public addition because the entries are hidden.

 

[uzzi38]

I wouldn't read much into it other than they actually thought they would release Alder Lake-S at one point. There's not much downside to leaving support in there in case they (yes) decide to revive it for whatever reason.

Nah, I'm fairly confident they'll launch something, and I'm also fairly confident it's either ADL-S or a really late Tiger Lake-S (either way it'll be mid-2021ish), but in either case it's stupid low volune and so mostly irrelevant.

It'll be there so they can claim the IPC crown on desktop and then crawl back into irrelevancy in the desktop space till late 2022, where a real comeback might take place.

Assuming no 7nm delays.

 

[uzzi38]

The addition of ADL is relatively new in public drivers, and it's not a public addition because the entries are hidden.

Imma add just a little bit of context here.

https://twitter.com/x/status/1200492732482932736

It's just a single reference for now. No need to go crazy over it, but something is certainly better than nothing.

 

[DrMrLordX]

It sounds like you can power down the off-die chips just as readily, but it never worked in practice.

Hmm, makes me wonder how viable EMIB will ever be if Intel continues having such problems. AMD doesn't even seem to try.

It'll be there so they can claim the IPC crown on desktop and then crawl back into irrelevancy in the desktop space till late 2022, where a real comeback might take place.

If Alder Lake does show up in late 2021, it won't be claiming any IPC crowns.

 

[uzzi38]

Hmm, makes me wonder how viable EMIB will ever be if Intel continues having such problems. AMD doesn't even seem to try.



If Alder Lake does show up in late 2021, it won't be claiming any IPC crowns.

It will claim the IPC crown. Golden Cove should not be underestimated, whereas Zen 4 is not as IPC focused as Zen 3 is. Zen 4 will likely just edge out Willow Cove for IPC.

By how much will it have that crown? Eh... can't say. I'm expecting by about 10% or so, depending on Zen 4 more than anything else.

That's only IPC though. Intel will still have a yield issue and a significant core count deficit against them. Though by ADL-S clocks will be in a much, much better state as well.

It's worth noting though that the IPC estimate I have for Zen 3 I might be underselling, but I have a good reason to do so.

 

[DrMrLordX]

@uzzi38

What makes you think Alder Lake-S uses Golden Cove? I thought Intel wasn't introducing Golden Cove until 7nm was ready. Everything else on 10nm is using Willow cove: Tiger Lake, Sapphire Rapids. Lakefield actually uses Sunny Cove.

 

[mikk]

If Alder Lake does show up in late 2021, it won't be claiming any IPC crowns.

I doubt AMD is able to reach Golden Cove IPC in 2021. Intel currently has a 18% IPC lead over AMD with Sunny Cove. Next year it will probably increase to about 25% with Willow Cove. AMD should decrease the deficit with Zen 3 but they surely won't close down the gap. Golden Cove should bring another huge leap over Willow Cove. AMD would need two IPC steps with Zen4 in one generation to close the gap. Some people seem to forget that Intel has a manufacturing problem and not a design problem.

 

[uzzi38]

...uh, is Golden Cove for Alder Lake NOT confirmed?

I could have sworn it was...