Ice Lake timeliness is promising. Ice Lake architecture is unknown, but it's been in the works for a while; likely a refinement of Skylake, nothing drastic or revolutionary. Gen 11 graphics tho?
Looking forward to seeing Ice Lake-S 8-core.
Ice Lake seems to have a bigger L1D cache, which could be indicative of bigger changes elsewhere in the core. You don't make changes to the L1D cache like that, esp. given how long Intel has stuck with that size, unless the rest of the machine would've been bottlenecked w/o the change, IMO.
Here are my predictions for the Ice Lake core changes:
- Increase the size of the uOp cache and allow for >6 uOps to be sent to the uOp queue from this cache per cycle.
- Widen decode; SKL can issue 5 uOps from the legacy decode pipeline (it uses 4 hardware decoders but with "tricks" to get a peak of 5 uOps), but I think they'll add an additional decoder.
- To take advantage of wider instruction supply in the front end, I expect Intel to go from an 8-wide backend to a 10-wide backend (similar to Zen), though I'd expect the schedule to remain unified rather than a split Int/FP as in the Zen uArch.
- A return to an 8-way associative L2 cache. Intel says that they saved power by going from 8-way to 4-way and this also helped with SKX (allowing the 768KB cache to be "tacked on" more easily), and they even claim no perf hit, but I think that this is wrong and it's part of the reason why SKL-S did not deliver more IPC over BDW client than it really should've (Intel seems to have been aiming for 10-15% based on the increases in the various OoO structures). With 10nm+ power consumption should come down a lot allowing for the higher cache associativity (increased hit rate in the L2 cache).
- Standard 10-15% increases in the sizes of the various buffers (OoO window, in-flight loads/stores, scheduler size, PRF sizes, and allocation queue).
. I realize that 6 to 8 is a smaller relative jump than 4 to 6, but still.
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